Structure and method for forming field effect transistor with low resistance channel region

• US 7,943,993 B2
• Filed: 09/27/2010
• Issued: 05/17/2011
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James, Wang, Qi
• Primary Examiner(s): Mandala; Victor
• Application Number:
  US12/891,616
• Publication Number:
  US 20110012174A1
• Time in Patent Office: 232 Days
• Field of Search: 257/330, 257/331, 257/332, 257/E29.257, 438/430, 438/337
• US Class Current: 257/332
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.

Claims

1. A trench-gate field effect transistor comprising:

trenches extending into a silicon region of a first conductivity type;

a gate electrode in each trench;

body regions of a second conductivity type extending over the silicon region between adjacent trenches, each body region forming a PN junction with the silicon region;

a gate dielectric layer lining at least upper sidewalls of each trench, the gate dielectric layer insulating the gate electrode from the body region;

source regions of the first conductivity flanking the trenches; and

a silicon-germanium region vertically extending through each source region and through a corresponding body region, the silicon-germanium region terminating within the corresponding body region before reaching the PN junction.

2. The transistor of claim 1 wherein each silicon-germanium region is spaced from the corresponding PN junction a distance in the range of 500 Å

to 1,000 Å

.

3. The transistor of claim 1 wherein each silicon-germanium region is bounded along its vertical boundaries by silicon regions.

4. The transistor of claim 1 wherein when the transistor is in an on state, a channel region is formed in the body region along each trench sidewall between each source region and a bottom surface of a corresponding body region, and the silicon-germanium region forms at least a part of the channel region so as to reduce the channel resistance.

5. The transistor of claim 1 wherein each trench includes silicon material insulated from the gate electrode therein.

6. The transistor of claim 1 wherein the silicon-germanium regions are disposed inside the trenches.

7. The transistor of claim 1 wherein the transistor is an P-channel transistor with the first conductivity type being P-type and the second conductivity type being N-type.

8. The transistor of claim 1 wherein each trench further includes:

a shield dielectric layer thicker than the gate dielectric lining lower sidewalls of the trench;

a shield electrode in a lower portion of the trench under the gate electrode; and

an inter-electrode dielectric layer insulating the gate and shield electrodes from one another.

9. The transistor of claim 1 wherein each trench includes a thick bottom dielectric along the trench bottom below the gate electrode.

10. A method of forming a trench-gate field effect transistor, comprising:

forming trenches extending into a silicon region of a first conductivity type;

forming body regions of a second conductivity such that each body region forms a PN junction with the silicon region, and each body region includes a vertically extending silicon-germanium layer;

forming a gate electrode in each trench; and

forming source regions of the first conductivity flanking the trenches,

wherein the silicon-germanium layers terminate along the vertical dimension before reaching the PN junction.

11. The method of claim 10 wherein each silicon-germanium layer is spaced from the corresponding PN junction a distance in the range of 500 Å

to 1,000 Å

.

12. The method of claim 10 wherein each silicon-germanium layer is bounded along its vertical boundaries by silicon regions.

13. The method of claim 10 wherein when the transistor is in an on state, a channel region is formed in the body region along each trench sidewall between each source region and a bottom surface of a corresponding body region, and the silicon-germanium layer forms at least a part of the channel region so as to reduce the channel resistance.

14. The method of claim 10 wherein the step of forming body regions includes:

forming a dielectric layer in each trench;

lining upper trench sidewalls with a silicon-germanium layer over the dielectric layer;

recessing the dielectric layer to expose a portion of each trench sidewall directly below the silicon-germanium layer;

forming an epitaxial silicon layer inside the trench such that the epitaxial layer lines the exposed portion of each trench sidewall; and

implanting dopants of the second conductivity type into the silicon region, the silicon-germanium layer and the epitaxial silicon layer to thereby form the body region.

15. The method of claim 10 wherein the silicon-germanium regions are formed inside the trenches.

16. The method of claim 10 wherein the transistor is an P-channel transistor with the first conductivity type being P-type and the second conductivity type being N-type.

17. The method of claim 10 further comprising:

before forming the gate electrode;

forming a shield dielectric layer lining lower sidewalls of each trench;

forming a shield electrode in a lower portion of each trench; and

forming an inter-electrode dielectric layer over the shield electrode in each trench.

18. The method of claim 10 further comprising:

before forming the gate electrode, forming a thick bottom dielectric along a bottom of each trench.