Method and apparatus for providing a tester integrated circuit for testing a semiconductor device under test

• US 7,944,225 B2
• Filed: 09/26/2008
• Issued: 05/17/2011
• Est. Priority Date: 09/26/2008
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Kemmerling, Todd Ryland
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Nguyen; Tung X
• Application Number:
  US12/239,326
• Publication Number:
  US 20100079159A1
• Time in Patent Office: 963 Days
• Field of Search: 324/765, 324/754, 324761-762, 324/760, 324/158.1, 257/48, 438 14- 18
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

Methods and apparatus for providing a tester integrated circuit (IC) for testing a semiconductor device under test (DUT) are described. Examples of the invention can relate to an apparatus for testing a semiconductor device under test (DUT). In some examples, the apparatus can include an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits.

Claims

1. Apparatus for testing a semiconductor device under test (DUT), comprising:

an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits by selectively connecting the at least one of the dedicated test circuits to at least one of the test probes while selectively disconnecting at least another one of the dedicated test circuits from the test probes,

wherein each of a plurality of the dedicated test circuits is configured to perform a different test on the DUT.

6. The apparatus of claim 1, wherein the programmable logic includes a processor, and wherein the dedicated test circuits are coupled to a bus interface of the processor.

7. The apparatus of claim 6, wherein the processor communicates with a memory, and wherein the programming data includes instructions stored in the memory and being executable by the processor.

21. The apparatus of claim 1, wherein one or more of the at least one of the dedicated test circuits selectively connected to the at least one of the test probes is configured to perform a different test on the DUT than one or more of the at least another one of the dedicated test circuits selectively disconnected from the test probes.

2. Apparatus for testing a semiconductor device under test (DUT), comprising:

an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits,

wherein the programmable logic comprises a programmable interconnect fabric, and wherein the dedicated test circuits are coupled to input/output (IO) ports of the programmable interconnect fabric.

3. The apparatus of claim 2, wherein the programmable interconnect fabric includes a configuration memory, and wherein the programming data includes configuration data, stored in the configuration memory, for controlling programmable interconnections of conductor segments in the programmable interconnect fabric.

4. The apparatus of claim 3, wherein the programmable logic further comprises a processor coupled to the IO ports of the programmable interconnect fabric.

5. The apparatus of claim 4, wherein the processor is configured to control storage of the configuration data in the configuration memory.

8. Apparatus for testing a semiconductor device under test (DUT), comprising:

a probe card assembly having input terminals coupled to test probes via signal paths, the test probes configured to contact pads on the DUT; and

test instruments, coupled to the input terminals, the test instruments including at least one tester integrated circuit (IC), each of the at least one tester IC coupled to one or more of the input terminals and including;

a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits by selectively connecting the at least one of the dedicated test circuits to at least one of the test probes while selectively disconnecting at least another one of the dedicated test circuits from the test probes,

wherein each of a plurality of the dedicated test circuits is configured to perform a different test on the DUT.

13. The apparatus of claim 8, wherein the programmable logic includes a processor, and wherein the dedicated test circuits are coupled to a bus interface of the processor.

14. The apparatus of claim 13, wherein the processor communicates with a memory, and wherein the programming data includes instructions stored in the memory and being executable by the processor.

22. The apparatus of claim 8, wherein one or more of the at least one of the dedicated test circuits selectively connected to the at least one of the test probes is configured to perform a different test on the DUT than one or more of the at least another one of the dedicated test circuits selectively disconnected from the test probes.

9. Apparatus for testing a semiconductor device under test (DUT), comprising:

an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits,

wherein the programmable logic comprises a programmable interconnect fabric, and wherein the dedicated test circuits are coupled to input/output (TO) ports of the programmable interconnect fabric.

10. The apparatus of claim 9, wherein the programmable interconnect fabric includes a configuration memory, and wherein the programming data includes configuration data, stored in the configuration memory, for controlling programmable interconnections of conductor segments in the programmable interconnect fabric.

11. The apparatus of claim 10, wherein the programmable logic further comprises a processor coupled to the IO ports of the programmable interconnect fabric.

12. The apparatus of claim 11, wherein the processor is configured to control storage of the configuration data in the configuration memory.

15. A probe card assembly, comprising:

signal paths coupled to test probes, the test probes configured to contact pads on a semiconductor device under test (DUT); and

at least one tester integrated circuit (IC) coupled one or more of the signal paths and including;

a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits by selectively connecting the at least one of the dedicated test circuits to at least one of the test probes while selectively disconnecting at least another one of the dedicated test circuits from the test probes,

wherein each of a plurality of the dedicated test circuits is configured to perform a different test on the DUT.

19. The probe card assembly of claim 15, wherein the programmable logic includes a processor, and wherein the dedicated test circuits are coupled to a bus interface of the processor.

20. The probe card assembly of claim 19, wherein the processor communicates with a memory, and wherein the programming data includes instructions stored in the memory and being executable by the processor.

23. The probe card assembly of claim 15, wherein one or more of the at least one of the dedicated test circuits selectively connected to the at least one of the test probes is configured to perform a different test on the DUT than one or more of the at least another one of the dedicated test circuits selectively disconnected from the test probes.

16. Apparatus for testing a semiconductor device under test (DUT), comprising:

an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits,

wherein the programmable logic comprises a programmable interconnect fabric, and wherein the dedicated test circuits are coupled to input/output (IO) ports of the programmable interconnect fabric.

17. The probe card assembly of claim 16, wherein the programmable interconnect fabric includes a configuration memory, and wherein the programming data includes configuration data, stored in the configuration memory, for controlling programmable interconnections of conductor segments in the programmable interconnect fabric.

18. The probe card assembly of claim 17, wherein the programmable logic further comprises a processor coupled to the IO ports of the programmable interconnect fabric.