Solid-state image-pickup device including unit pixels having a 3-transistor design and wherein a vertical selection pulse provides a reset potential

• US 7,944,491 B2
• Filed: 09/20/2004
• Issued: 05/17/2011
• Est. Priority Date: 06/08/1998
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yonemoto, Kazuya, Ueno, Takahisa, Shiono, Koichi, Suzuki, Ryoji
• Primary Examiner(s): WHIPKEY, JASON T
• Application Number:
  US10/945,503
• Publication Number:
  US 20050036050A1
• Time in Patent Office: 2,430 Days
• Field of Search: 348/308, 348/302, 348/294, 257/292, 257/291, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/441 by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

Since the great number of elements constituting a unit pixel having an amplification function would hinder reduction of pixel size, unit pixel n,m arranged in a matrix form is comprised of a photodiode, a transfer switch for transferring charges stored in the photodiode, a floating diffusion for storing charges transferred by the transfer switch, a reset switch for resetting the floating diffusion, and an amplifying transistor for outputting a signal in accordance with the potential of the floating diffusion to a vertical signal line, and by affording vertical selection pulse φVn to the drain of the reset switch to control a reset potential thereof, pixels are selected in units of rows.

Claims

1. A solid-state imaging element, comprising:

unit pixels each of which includes a photoelectric conversion element, a transfer switch for transferring charge stored in said photoelectric conversion element, and a charge store part for storing charge transferred by said transfer switch, and a reset switch for resetting the charge store part;

wherein negative voltage is applied to a gate of said transfer switch for a period other than the period during which a charge transfer pulse is applied to the gate of the transfer switch to transfer charge stored in said photoelectric conversion element to said charge store part and wherein the application of the negative voltage to the transfer switch suppresses a dark current and further wherein a vertical selection pulse is actively driven to a low level in order to further suppress the dark current; and

further wherein said unit pixels each include an overflow path at an area to which a pixel source voltage is applied, said overflow path being used to discharge excess charges of said photoelectric conversion element and being comprised of a modified semiconductor portion selectively providing a reduced barrier to charge migration relative to regions adjacent thereto.

2. The solid-state imaging element as claimed in claim 1, further including a vertical scanning circuit that outputs vertical selection pulses during vertical scanning to the reset switch as a reset potential thereof.

3. The solid-state imaging element as claimed in claim 1, wherein said charge store part is a floating diffusion region.

4. The solid-state imaging element as claimed in claim 1, further comprising a reset transistor, and wherein the reset transistor is a depletion type transistor.

5. The solid-state imaging element as claimed in claim 1, wherein an output circuit outputs signals from vertical signal lines in voltage mode.

6. The solid-state imaging element as claimed in claim 1, wherein an output circuit outputs signals from vertical signal lines in current mode.

7. The solid-state imaging element as claimed in claim 2, wherein each of said unit pixels includes a transfer selection switch for selecting a transfer operation of said transfer switches.

8. The solid-state imaging element as claimed in claim 7, wherein said transfer selection switch has a gate terminal that receives said vertical selection pulses.

9. The solid-state imaging element as claimed in claim 7, wherein an output circuit outputs signals from vertical signal lines in current mode.

10. A solid-state imaging element as claimed in claim 7, wherein an output circuit outputs signals from vertical signal lines in voltage mode.

11. The solid-state imaging element as claimed in claim 7, wherein the application of the negative voltage to the transfer switch suppresses a dark current.

12. The solid-state imaging element as claimed in claim 2, wherein a falling edge of the reset pulse triggers reading of a reference level.

13. The solid-state imaging element as claimed in claim 2, wherein a changing state of the reset pulse and a selection pulse initiates a pixel reading operation.