Programming a memory cell with a diode in series by applying reverse bias

• US 7,944,728 B2
• Filed: 12/19/2008
• Issued: 05/17/2011
• Est. Priority Date: 12/19/2008
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Nian, Yibo, Scheuerlein, Roy E., Kumar, Tanmay
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US12/318,021
• Publication Number:
  US 20100157652A1
• Time in Patent Office: 879 Days
• Field of Search: 365/148, 365/163, 365/158, 365/171, 365/173, 365/189.16
• US Class Current: 365/148
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5664 using organic memory material storage elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode

Abstract

A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from a first initial state to a second state different from the first state.

Claims

1. A method of programming a memory cell comprising:

applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell, wherein the memory cell comprises a diode and a resistivity switching material element in series;

removing the temporary resistor; and

reading the state of the resistivity switching material element in the memory cell, wherein the state of the resistivity switching material element changes from a first initial state to a second state different from the first state.

2. The method of claim 1, further comprising:

applying a forward bias to the memory cell, without using the temporary resistor, to change the state of the resistivity switching material element from the second state substantially to the first state.

3. The method of claim 1, wherein the memory cell is part of a memory array.

4. The method of claim 3, wherein

the diode comprises a p-n semiconductor diode, a p-i-n semiconductor diode, a metal insulator metal (MIM) diode, or a metal insulator-insulator metal (MIIM) diode;

and

the resistivity switching storage element comprises a resistivity switching material selected from an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistance material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or a carbon resistivity switching material.

5. The method of claim 4, wherein the state of the resistivity switching material element changes substantially at a reverse bias threshold voltage.

6. The method of claim 5, wherein the reverse bias threshold voltage depends on diode reverse leakage characteristics of the diode and a threshold voltage required to set the resistivity switching material element.

7. The method of claim 6, wherein the reverse bias threshold voltage is approximately −

15 volts to −

25 volts across the temporary resistor, the diode, and the resistivity switching material element.

8. The method of claim 1, wherein the memory cell further comprises a second diode.

9. The method of claim 1, wherein the temporary resistor and the memory cell are located on the same die.

10. The method of claim 1, wherein the temporary resistor is not located on the same die as the memory cell.

11. The method of claim 10, wherein the temporary resistor is removed after programming the memory cell.

12. A method of programming a memory cell comprising:

applying a first reverse bias to the memory cell using a first temporary resistor in series with the memory cell, wherein the memory cell comprises a diode and a resistivity switching material element in series, and wherein the state of the resistivity switching material element changes from a first initial state to a second state different from the first state;

applying a second reverse bias to the memory cell using a second temporary resistor in series with the memory cell, wherein the state of the resistivity switching material element changes from the second state to a third state different from the second state, and wherein the first temporary resistor and the second temporary resistor have different resistances;

applying a third reverse bias to the memory cell using a third temporary resistor in series with the memory cell, wherein the state of the resistivity switching material element changes from the third state to a fourth state different from the third state;

removing the temporary resistors; and

reading the state of the resistivity switching material element in the memory cell;

wherein the first temporary resistor, the second temporary resistor, and the third temporary resistor have different resistances;

wherein the first state, the second state, the third state, and the fourth state are different from each other;

wherein the first state corresponds to a first data value, the second state corresponds to a second data value, the third state corresponds to a third data value, and the fourth state corresponds to a fourth data value; and

wherein the memory cell is part of a memory cell array.

13. The method of claim 12, wherein the temporary resistors are not located on the same die as the memory cell.

14. The method of claim 12, further comprising:

applying a forward bias to the memory cell, without using one of the temporary resistors, to change the state of the resistivity switching material element to substantially the first state.