Non-volatile memory control

• US 7,944,762 B2
• Filed: 05/08/2007
• Issued: 05/17/2011
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gorobets, Sergey Anatolievich
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/800,974
• Publication Number:
  US 20070274150A1
• Time in Patent Office: 1,470 Days
• Field of Search: 365/194, 365/189.04, 365/239
• US Class Current: 365/194
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.

Claims

1. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit.

2. The method of claim 1, wherein the operation is selected from the group consisting of a read operation, a programming operation and an erase operation.

4. The method of claim 1, further comprising introducing delay to the operation even though the memory system is capable of concurrent access of a number of memory arrays in excess of the allowed limit.

10. The method of claim 1, further comprising:

receiving the allowed limit from a host coupled to the memory system.

3. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein determining the number of active memory arrays comprises polling each of the memory arrays or checking independent ready/busy signals for each of the memory arrays.

5. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein introducing delay to the operation comprises holding data transfer to a memory array during a programming operation while the number of active memory arrays is at the allowed limit.

6. The method of claim 5, wherein continuing with the operation comprises resuming data transfer to a memory array during the programming operation when the number of active memory arrays falls below the allowed limit.

7. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit;

continuing with the operation when the number of active memory arrays falls below the allowed limit; and

adjusting the allowed limit in response to electrical parameters for the operation.

8. The method of claim 7, wherein adjusting the allowed limit in response to electrical parameters for the operation comprises adjusting the allowed limit to maintain a desired electrical current level of the memory system during the operation.

9. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit;

continuing with the operation when the number of active memory arrays falls below the allowed limit; and

adjusting the allowed limit in response to electrical parameters for each operation of the memory system accessing two or more of the memory arrays of the memory system.

11. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein initiating the operation for access of two or more memory arrays of the memory system comprises initiating an operation to sequentially and cyclically access the two or more memory arrays, and wherein an individual access operation of one memory array is permitted to begin while an individual access operation of a different memory array is still active.

12. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein initiating the operation for access of two or more memory arrays of the memory system comprises initiating an operation to sequentially and cyclically access the two or more memory arrays, and wherein an individual access operation of one memory array is permitted to begin while an individual access operation of a different memory array is still active; and

wherein initiating the operation to sequentially and cyclically access the two or more memory arrays comprises;

beginning an individual access operation of a physical sector of a first memory array;

while the individual access operation of the first physical sector is still active, beginning an individual access operation of a physical sector of a second memory array; and

while the individual access operations of the first and second physical sectors are still active, beginning an individual access operation of a physical sector of a third memory array.

13. The method of claim 12, further comprising:

waiting to begin an individual access operation of a physical sector of a fourth memory array until completion of the individual access operation of the physical sector of the first memory array.

14. A method of operating a memory system, comprising:

initiating an operation for access of two or more memory arrays of the memory system;

determining a number of active memory arrays of the memory system during the operation;

introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein initiating the operation for access of two or more memory arrays of the memory system comprises initiating an operation to sequentially and cyclically access the two or more memory arrays, and wherein an individual access operation of one memory array is permitted to begin while an individual access operation of a different memory array is still active;

wherein the two or more memory arrays are partitioned into N virtual blocks, each virtual block comprising a physical block of memory storage cells in each of the two or more memory arrays, and each physical block comprising a plurality of physical sectors of memory storage cells; and

wherein initiating an operation to sequentially and cyclically access the two or more memory arrays comprises sequentially accessing a first physical sector in each of the memory arrays of a virtual block and, following accessing the first physical sector in a last memory array of the virtual block, accessing a second physical sector in a first memory array of the virtual block.

15. A memory system, comprising:

a non-volatile memory comprising a plurality of memory arrays, each memory array comprising a plurality of memory storage cells;

a controller; and

a physical interface coupled between the non-volatile memory and the controller;

wherein the controller is configured to perform a method, the method comprising;

initiating an operation for access of two or more memory arrays of the non-volatile memory;

determining a number of active memory arrays of the non-volatile memory during the operation;

pausing the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit.

17. The memory system of claim 15, wherein the controller is further configured to check independent ready/busy signals for each of the memory arrays to determine the number of active memory arrays.

18. The memory system of claim 15, wherein the controller is further configured to pause the operation even though the controller is capable of concurrent access of a number of memory arrays in excess of the allowed limit.

23. The memory system of claim 15, wherein available operations for the controller include read operations, programming operations and erase operations.

24. The memory system of claim 23, wherein the controller is configured to program the allowed limit for each of the available operations to maintain a desired electrical current level of the memory system.

25. The memory system of claim 15, wherein the controller is further coupled to a host and wherein the controller is further configured to receive the allowed limit from the host for the operation.

26. The memory system of claim 25, wherein the host is configured to provide the allowed limit to the controller in response to power management features of the host.

16. A memory system, comprising:

a non-volatile memory comprising a plurality of memory arrays, each memory array comprising a plurality of memory storage cells;

a controller; and

a physical interface coupled between the non-volatile memory and the controller;

wherein the controller is configured to perform a method, the method comprising;

initiating an operation for access of two or more memory arrays of the non-volatile memory;

determining a number of active memory arrays of the non-volatile memory during the operation;

pausing the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein the controller is further configured to poll each of the memory arrays to determine the number of active memory arrays.

19. A memory system, comprising:

a non-volatile memory comprising a plurality of memory arrays, each memory array comprising a plurality of memory storage cells;

a controller; and

a physical interface coupled between the non-volatile memory and the controller;

wherein the controller is configured to perform a method, the method comprising;

initiating an operation for access of two or more memory arrays of the non-volatile memory;

determining a number of active memory arrays of the non-volatile memory during the operation;

pausing the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein pausing the operation comprises discontinuing data transfer to or from the non-volatile memory.

20. The memory system of claim 19, wherein continuing with the operation comprises resuming data transfer to or from the non-volatile memory.

21. A memory system, comprising:

a non-volatile memory comprising a plurality of memory arrays, each memory array comprising a plurality of memory storage cells;

a controller; and

a physical interface coupled between the non-volatile memory and the controller;

wherein the controller is configured to perform a method, the method comprising;

initiating an operation for access of two or more memory arrays of the non-volatile memory;

determining a number of active memory arrays of the non-volatile memory during the operation;

pausing the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein the allowed limit is programmable.

22. The memory system of claim 21, wherein the controller is further configured to program the allowed limit to maintain a desired electrical current level of the memory system during the operation.

27. A memory system, comprising:

a non-volatile memory comprising a plurality of memory arrays, each memory array comprising a plurality of memory storage cells;

a controller; and

a physical interface coupled between the non-volatile memory and the controller;

wherein the controller is configured to perform a method, the method comprising;

initiating an operation for access of two or more memory arrays of the non-volatile memory;

determining a number of active memory arrays of the non-volatile memory during the operation;

pausing the operation if the number of active memory arrays has reached an allowed limit; and

continuing with the operation when the number of active memory arrays falls below the allowed limit;

wherein the controller is further configured to initiate the operation to sequentially and cyclically access the two or more memory arrays, wherein the operation to access the two or more memory arrays comprises a series of individual access operations of the two or more memory arrays, and wherein an individual access operation of one memory array is permitted to begin while an individual access operation of a different memory array is still active.

28. The memory system of claim 27, further comprising:

wherein the two or more memory arrays are partitioned into N virtual blocks, each virtual block comprising a physical block of memory storage cells in each of the two or more memory arrays, and each physical block comprising a plurality of physical sectors of memory storage cells; and

wherein the controller is further configured to initiate the operation to sequentially and cyclically access the two or more memory arrays comprising sequentially accessing a first physical sector in each of the memory arrays of a virtual block and, following accessing the first physical sector in a last memory array of the virtual block, accessing a second physical sector in a first memory array of the virtual block.