Method of digital extraction for accurate failure diagnosis

• US 7,945,417 B2
• Filed: 01/03/2008
• Issued: 05/17/2011
• Est. Priority Date: 07/30/2007
• Status: Expired due to Fees

• Current Assignee: Carl Z. Zhou
• Original Assignee: Carl Z. Zhou
• Inventors: Vohra, Fazela M., Zhou, Carl Z.
• Primary Examiner(s): Feliciano; Eliseo Ramos
• Assistant Examiner(s): Suarez; Felix E
• Application Number:
  US11/968,997
• Publication Number:
  US 20090033335A1
• Time in Patent Office: 1,230 Days
• Field of Search: 702/59, 702/84, 702/117, 702/118, 702/120, 702/181, 702/182, 324/537, 703/2, 703/15, 714/738, 714/744
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

A method for testing VLSI circuits comprises a two-pass diagnostic method for testing a circuit wherein a first pass comprises a conventional test flow wherein an ATPG tool generates a set of test patterns and identifies possible faulty nets within the circuit. A second pass focuses on a designated critical subset of the circuit extracted using a method for extracting a subset for failure diagnosis of the tested circuit. A second pass utilizes an extraction algorithm which extracts one or more critical subsets of the circuit in order to obtain more accurate failure diagnosis.

Claims

1. A method for testing Very Large Scale Integration circuits, the method comprising:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm comprising the steps of;

a) providing a synthesized, full scan netlist of the original circuit;

b) providing a possible candidate fault list which contains each existing fault within the circuit, each existing fault having a gate name and position;

c) assigning net types to all nets within the original circuit, the net types selected from the group consisting of Core (C), extended (E), to be decided (D), can be passivated (P), and can be ignored (X);

d) assigning net attributes for all type (P) and (D) nets;

e) converting assigned type (P) and (D) nets to either type (E) or (X) nets;

f) re-assigning net attributes to converted nets; and

g) repeating steps e) and f) until all type (D) nets are converted to either type (E) or (X) nets and all type (P) nets have net possibility attributes indicating that a net path logic can be set without conflicts (Y);

extracting a reduced circuit from the defined subset according to the provided extraction algorithm, the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and

passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit;

wherein the net types are assigned to all nets within the original circuit according to a method comprising the steps of;

a) assigning net type (C) to all interested nets;

b) assigning net type (E) to any unassigned nets that are the output nets of gates whose input nets contain (C) or (E) nets;

c) assigning net type (D) to any unassigned nets that are multiple output nets of a stem whose input net is (C) or (E) net;

d) assigning net type (D) to any unassigned nets for which the net'"'"'s upstream nets contain (D) nets;

e) assigning net type (E) to any unassigned net that is the sole input of a stem or a gate whose outputs contain (C) or (E) nets;

f) assigning net type (P) to any unassigned nets that are input nets of gates whose outputs are (C), (E), or (D) nets;

g) assigning net type (P) to any unassigned nets whose downstream nets contain (P) nets; and

h) assigning net type (X) to any remaining unassigned nets.

2. A method for testing Very Large Scale Integration circuits, the method comprising:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm comprising the steps of;

a) providing a synthesized, full scan netlist of the original circuit

b) providing a possible candidate fault list which contains each existing fault within the circuit, each existing fault having a gate name and position;

c) assigning net types to all nets within the original circuit, the net types selected from the group consisting of Core (C), extended (E), to be decided (D), can be passivated (P), and can be ignored (X);

d) assigning net attributes for all type (P) and (D) nets;

e) converting assigned type (P) and (D) nets to either type (E) or (X) nets;

f) re-assigning net attributes to converted nets; and

g) repeating steps e) and f) until all type (D) nets are converted to either type (E) or (X) nets and all type (P) nets have net possibility attributes indicating that a net path logic can be set without conflicts (Y);

extracting a reduced circuit from the defined subset according to the provided extraction algorithm, the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and

passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit;

wherein the net attributes are assigned to all type (P) nets according to a method comprising the steps of;

a) assigning source attribute (E) to any (P) nets which are inputs of gates whose outputs are either (C) or (E) nets;

b) assigning source attribute (D) to any (P) nets which are inputs of gates whose outputs are (D) nets;

c) assigning source attribute (E) to any (P) nets with downstream (P) nets having source attribute (E);

d) assigning source attribute (D) to any (P) nets with downstream (P) nets having source attribute (D);

e) assigning value attribute one (1) to (P) nets which are inputs of AND or NAND gates whose outputs are (C), (E), or (D) nets;

f) assigning value attribute zero (0) to (P) nets which are inputs of OR or NOR gates whose outputs are (C), (E), or (D) nets;

g) for (P) nets that are inputs of gates whose outputs are (P) nets, assigning value attributes so that when the input (P) nets'"'"' logic states are set as the input (P) net value attributes, the output (P) nets are at the logic states as indicated by the output (P) net value attributes;

h) for any (P) net that is an input of a stem, assigning the same value attribute as that of the output (P) nets if all output (P) nets have the same value attribute;

if output (P) nets have different value attributes, assigning the stem input (P) net value attribute zero (0) and one (1);

i) assigning value attribute zero (0) and one (1) to any (P) nets with downstream (P) net value attributes of zero (0) and one (1);

j) assigning possibility attribute (N) to (P) nets which are stem outputs and the corresponding stem inputs are (E) nets;

k) assigning possibility attribute (CE) to any (P) net which (1) is an output of a stem whose input (P) net has a value attribute of zero (0) and one (1) and (2) at least one of the stem output (P) nets with source attribute (E) has a value attribute different from its own value attribute;

l) assigning possibility attribute (CD) to any (P) net which (1) is an output of a stem whose input (P) nets have value attribute zero (0) and one (1), and (2) all stem output (P) nets that have different value attributes have source attribute (D);

m) assigning possibility attribute (N) to (P) nets with upstream (P) nets having possibility attribute (N);

n) assigning possibility attribute (CE) to (P) nets with upstream (P) nets having possibility attribute (CE) and with possibility attributes which have not been assigned in any of the previous steps a) through m);

o) assigning possibility attribute (CD) to (P) nets with upstream (P) nets having possibility attribute (CD) and with possibility attributes which have not been assigned in any of the previous steps a) through n);

p) assigning possibility attribute (C) to (P) nets having a value attribute of zero (0) and one (1) and with possibility attributes which have not been assigned in any of the previous steps a) through o);

q) assigning possibility attribute (Y) to any (P) nets whose possibility attributes have not been assigned in any of the previous steps a) through p).

3. A method for testing Very Large Scale Integration circuits, the method comprising:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm comprising the steps of;

a) providing a synthesized, full scan netlist of the original circuit

b) providing a possible candidate fault list which contains each existing fault within the circuit, each existing fault having a gate name and position;

c) assigning net types to all nets within the original circuit, the net types selected from the group consisting of Core (C), extended (E), to be decided (D), can be passivated (P), and can be ignored (X);

d) assigning net attributes for all type (P) and (D) nets;

e) converting assigned type (P) and (D) nets to either type (E) or (X) nets;

f) re-assigning net attributes to converted nets; and

g) repeating steps e) and f) until all type (D) nets are converted to either type (E)

or (X) nets and all type (P) nets have net possibility attributes indicating that a net path logic can be set without conflicts (Y);

extracting a reduced circuit from the defined subset according to the provided extraction algorithm, the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and

passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit;

wherein the net attributes are assigned to all type (D) nets according to a method comprising the steps of;

a) assigning difficulty attribute zero (0) to any (D) nets having paths which can reach primary or pseudo primary outputs without intersecting any other (C/E/D) net paths at gates and if all passivating (P) nets, if any, along the paths have possibility attribute (Y);

b) assigning difficulty attribute one (1) to any (D) nets having paths which can reach primary or pseudo primary outputs without intersecting any other (C/E/D) paths at gates and at least one of said (D) net'"'"'s passivated (P) nets has possibility attribute (CD) but none having possibility attribute (CE);

c) assigning difficulty attribute two (2) to any (D) nets having paths which can reach primary or pseudo primary outputs without intersecting any (C/E/D) paths at gates and at least one of said (D) net'"'"'s passivated (P) nets has possibility attribute (CE);

d) assigning difficulty attribute three (3) to any (D) nets having paths which can reach primary or pseudo primary outputs without intersecting any (C/E/D) paths at gates and at least one of said (D) net'"'"'s passivated (P) nets has possibility attribute (N);

e) assigning difficulty attribute four (4) to any (D) nets having paths which intersect with other (D) net paths at gates, but do not intersect with (C) or (E) nets at gates; and

f) assigning difficulty attribute five (5) to any (D) nets having paths which intersect with other (C) or (E) net paths at gates.

4. A method for testing Very Large Scale Integration circuits, the method comprising:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm comprising the steps of;

a) providing a synthesized, full scan netlist of the original circuit;

b) providing a possible candidate fault list which contains each existing fault within the circuit, each existing fault having a gate name and position;

c) assigning net types to all nets within the original circuit, the net types selected from the group consisting of Core (C), extended (E), to be decided (D), can be passivated (P), and can be ignored (X);

d) assigning net attributes for all type (P) and (D) nets;

e) converting assigned type (P) and (D) nets to either type (E) or (X) nets;

f) re-assigning net attributes to converted nets; and

g) repeating steps e) and f) until all type (D) nets are converted to either type (E)

or (X) nets and all type (P) nets have net possibility attributes indicating that a net path logic can be set without conflicts (Y);

extracting a reduced circuit from the defined subset according to the provided extraction algorithm, the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and

passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit;

wherein the nets are converted into a different net type according to a method comprising the steps of;

a) converting (D) nets with difficulty attribute of five (5) into (E) nets;

b) re-assigning net attributes according to a method for assigning net attributes;

c) repeating steps a) and b) until there are no remaining (D) nets with difficulty attribute of five (5);

d) converting any stem at which the input is a (C) or (E) net and some outputs are (D) nets, among which there is at least one (D) net path with difficulty attribute zero (0) according to a first conversion procedure comprising the steps of;

i. converting the (D) net path that least intersects with (P) nets among the paths of (D) nets having a difficulty attribute of zero (0) into (E) net path;

ii. converting all (D) net paths at the stem output with a difficulty attribute of four (4) into (P) nets; and

iii. converting all other remaining (D) net paths at the stem output along with said (D) nets'"'"' passivated (P) net paths into (X) net paths;

e) re-assigning net attributes as described in the procedures for assigning net attributes;

f) repeating steps d) and e) until there are no remaining (D) net paths with a difficulty attribute of zero (0);

g) converting any stem at which the stem'"'"'s input is a (C) or (E) net and some outputs are (D) nets among which at least one (D) net path has difficulty attribute value of one (1) according to a second conversion procedure comprising the steps of;

i. converting the (D) net path that least intersects with (P) nets among the difficulty attribute one (1) (D) net paths into an (E) net path;

ii. converting all (D) net paths at the stem output with a difficulty attribute of four (4) into (P) nets;

iii. converting all other (D) net paths at the stem output along with said (D) nets'"'"' passivated (P) net paths into (X) net paths;

h) re-assigning net attributes as described in the procedures for assigning net attributes;

i) repeating steps d) through h) until all (D) net paths have difficulty attributes larger than one (1);

j) converting any stem at which the stem'"'"'s input is a (C) or (E) net and some outputs are (D) nets among which there are at least one (D) net path with a difficulty attribute of two (2) according to a third conversion procedure comprising the steps;

i. converting the (D) net path that least intersects with (P) nets among the paths of (D) nets having a difficulty attribute of two (2) into an (E) net path;

ii. converting all (D) net paths at the stem output having a difficulty attribute of four (4) into (P) nets; and

iii. converting all other (D) net paths at the stem output along with said (D) nets'"'"' passivated (P) net paths into (X) net paths;

k) re-assigning net attributes as described in the procedures for assigning net attributes;

l) repeating steps d) through k) until all (D) net paths have difficulty attributes larger than two (2);

m) converting any stem at which the input is a (C) or (E) net and some outputs are (D) nets among which at least one (D) net path has a difficulty attribute value of three (3) according to a fourth conversion procedure comprising the steps of;

i. converting the (D) net path that least intersects with (P) nets among the paths of (D) nets having difficulty attribute three (3) into an (E) net path;

ii. converting all difficulty attribute four (4) (D) net paths at the stem output into (P) net paths; and

iii. converting all other remaining (D) net paths at the stem output along with said (D) nets'"'"' passivated (P) net paths into (X) net paths;

n) re-assigning net attributes as described in the procedures of for assigning net attributes;

o) repeating steps d) through n) until all (D) net paths have difficulty attributes larger than three (3);

p) converting all (D) nets into (E) nets;

q) re-assigning net attributes as described in the procedures for assigning net attributes;

r) converting any gate at which all inputs are (P) nets and the output is a (C) or (E) net, if there is at least one input (P) net having possibility attribute (Y), choose the (P) net path that intersects the least number of other (P) net paths among the possibility attribute (Y) (P) net paths into an (E) net path;

s) re-assigning net attributes as described in the procedures for assigning net attributes;

t) converting all (P) nets that have possibility attribute other than (Y) into (E) nets.