Memory hub with internal cache and/or memory access prediction

• US 7,945,737 B2
• Filed: 01/12/2009
• Issued: 05/17/2011
• Est. Priority Date: 06/07/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/352,053
• Publication Number:
  US 20090125688A1
• Time in Patent Office: 855 Days
• Field of Search: 711/137, 711/118, 711/154, 711/213, 711/145, 711/112, 711/113, 711/114, 711/E12.041, 711/E12.057, 710/22, 710/3, 710/100, 709/229, 709/250, 709/233, 709/104
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Claims

1. A memory system, comprising:

memory configured to store data in memory locations corresponding to memory addresses; and

a memory hub coupled to the memory and configured to receive memory access requests and having a memory interface coupled to the memory, the memory interface comprising;

a cache unit configured to store data;

a memory controller configured to receive the memory access requests, to access the memory, and in response, generate command and address signals to access memory locations in the memory identified in the memory request; and

a prediction unit configured to determine a predicted address for a memory location to be accessed in memory based on previous accesses to the memory and provide the same to the memory controller to generate command and address signals to access the memory location in memory corresponding to the predicted memory address.

2. The memory system of claim 1 wherein the memory comprises a plurality of random access memory devices.

3. The memory system of claim 1 wherein the memory hub further comprises a processor interface configured to interface with a processor.

4. The memory system of claim 3 wherein the memory hub further comprises a switch coupled to the processor interface and the memory interface.

5. The memory system of claim 1 wherein the memory system comprises a memory module.

6. The memory system of claim 1 wherein the prediction unit is configured to determine a predicted address for a memory location from which data, is to be read based on previous read operations to the memory.

7. The memory system of claim 6 wherein the memory controller is configured to generate command and address signals to read data from the memory location corresponding to the predicted memory address and store the read data in the cache unit.

8. A memory system, comprising:

a plurality of memory each configured to store data in memory locations corresponding to memory addresses;

a local memory controller coupled to the plurality of memory, the local memory controller having a plurality of memory interfaces each configured to interface with a respective one of the plurality of memory, each memory interface comprising;

a cache memory;

a prediction unit configured to predict a memory address of a memory location to access based on memory addresses of previously accessed memory locations; and

an interface memory controller coupled to the prediction unit and configured to receive the predicted memory address, the interface memory controller further configured to generate command and address signals for accessing the memory location in the respective memory corresponding to the predicted memory address in response to receiving the predicted memory address.

9. The memory system of claim 8 wherein the interface memory controller is configured to generate command and address signals to read data from the memory location in the respective memory corresponding to the predicted memory.

10. The memory system of claim 9 wherein the interface memory controller is further configured to store the read data from the memory location corresponding to the predicted memory in the cache memory.

11. The memory system of claim 8 wherein the plurality of memory comprises a plurality of dynamic random access memory devices.

12. The memory system of claim 11 wherein the memory system is a memory module.

13. The memory system of claim 8 wherein the local memory controller further comprises a processor interface configured to interface with a processor.

14. The memory system of claim 8 wherein the interface memory controller is further configured to store data read from the memory location corresponding to the predicted memory address in the cache memory.

15. A method for accessing memory locations in memory corresponding to memory addresses, the method comprising:

receiving at a memory hub an external memory command to access memory to which the memory hub is coupled;

accessing a memory location in memory identified by the external memory request;

within the memory hub, predicting a memory address for a memory location to be accessed based on prior memory accesses to the memory; and

accessing the memory location corresponding to the predicted memory address without receiving an external memory commands identifying the accessed memory location.

16. The method of claim 15 wherein accessing the memory location corresponding to the predicted memory address comprises reading data from the memory location corresponding to the predicted memory address.

17. The method of claim 16, further comprising storing the data read from the memory location corresponding to the predicted memory address in a cache memory.

18. The method of claim 15 wherein predicting a memory address for a memory, location to be accessed based on prior memory accesses to the memory comprises predicting a memory address for a memory location to be accessed based on prior memory write operations to the memory.

19. The method of claim 15 wherein accessing a memory location in memory identified by the external memory request comprises accessing a memory location in a dynamic random access memory device.