Storage array partitioning

• US 7,945,758 B1
• Filed: 03/29/2007
• Issued: 05/17/2011
• Est. Priority Date: 03/29/2007
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Veprinsky, Alexandr, Michael, Ofer E., Scharland, Michael J.
• Primary Examiner(s): Gu; Shawn X
• Application Number:
  US11/729,716
• Time in Patent Office: 1,510 Days
• Field of Search: None
• US Class Current: 711/173
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A storage array includes a plurality of directors, each having at least one processor thereon and a global memory distributed among the plurality of directors. A different portion of the global memory is provided on each of the directors. A interconnect fabric is coupled to each of the directors. Global memory accesses performed by one director to access memory of another director through the interconnect fabric. The storage array also includes a plurality of partitioned storage subsystems, each including a separate subset of the directors, where each of the partitioned storage subsystems handles I/O operations for a plurality of logical devices independently of I/O operations for logical devices of other ones of the partitioned storage subsystems, the I/O operations using metadata provided in the global memory of the corresponding directors and containing information that correlates logical device data with physical device data.

Claims

1. A storage array, comprising:

a plurality of directors, each having at least one processor thereon;

a global memory distributed among the plurality of directors, wherein a portion of the global memory is provided on each of the directors, and wherein the portion of the global memory on each director is accessible by other of the directors;

a interconnect fabric coupled to each of the directors, wherein global memory accesses performed by one director to access the portion of the global memory provided on another director are through the interconnect fabric;

a plurality of partitioned storage subsystems, each including a separate subset of the directors, wherein each of the partitioned storage subsystems handles I/O operations for a plurality of logical devices independently of other I/O operations for logical devices of other ones of the partitioned storage subsystems; and

a mechanism that, for each of the I/O operations, determines a particular one of the partitioned storage subsystems to handle a particular one of the I/O operations, wherein the particular one of the partitioned storage subsystems is determined according to metadata that is provided in the portion of the global memory provided on a corresponding director that corresponds to the particular one of the I/O operations, wherein the corresponding director is included in the particular one of the partitioned storage subsystems, wherein the metadata contains information that correlates logical device data with physical device data, and wherein the mechanism transfers a handling request for the particular one of the I/O operations to the particular one of the partitioned storage subsystems.

2. A storage array, according to claim 1, wherein the physical device data is provided by at least one disk drive coupled to at least one of the directors.

3. A storage array, according to claim 1, further comprising:

a local memory, provided on each of the directors, wherein each local memory is accessed exclusively by the at least one processor of a corresponding one of the directors.

4. A storage array, according to claim 1, wherein the metadata includes device tables and cache slots.

5. A storage array, according to claim 1, wherein the interconnect fabric is implemented using an Internet Protocol (IP) network.

6. A storage array, according to claim 1, wherein memory accesses are performed using Direct Memory Access (DMA).

7. A storage array, according to claim 6, wherein each of the directors includes a interconnect fabric interface and wherein each interconnect fabric interface includes Direct Memory Access (DMA) hardware.

8. A storage array, comprising:

a plurality of directors, each having at least one processor thereon;

a global memory distributed among the plurality of directors, wherein a portion of the global memory is provided on each of the directors, and wherein the portion of the global memory on each of the directors is accessible by other of the directors;

a interconnect fabric coupled to each of the directors, wherein global memory accesses performed by one director to access the portion of the global memory provided on another director are through the interconnect fabric;

metadata for logical devices, provided in the global memory, wherein the metadata contains information that correlates logical device data with physical device data; and

a mechanism that, for a particular I/O operation, determines a corresponding director of the storage array to handle the particular I/O operation, wherein the corresponding director of the storage array is determined according to a portion of the metadata that is provided in the portion of the global memory provided on the corresponding director, wherein the portion of the metadata provided on the corresponding director corresponds to the I/O operation, and wherein the mechanism transfers a handling request for the particular I/O operation to the corresponding director.

9. A storage array, according to claim 8, wherein the physical device data is provided by at least one disk drive coupled to at least one of the directors.

10. A storage array, according to claim 8, further comprising:

a local memory, provided on each of the directors, wherein each local memory is accessed exclusively by the at least one processor of a corresponding one of the directors.

11. A storage array, according to claim 8, wherein the metadata includes device tables and cache slots.

12. A storage array, according to claim 8, wherein the interconnect fabric is implemented using an Internet Protocol (IP) network.

13. A storage array, according to claim 8, wherein memory accesses are performed using Direct Memory Access (DMA).

14. A storage array, according to claim 13, wherein each of the directors includes a interconnect fabric interface and wherein each interconnect fabric interface includes Direct Memory Access (DMA) hardware.

15. A director for a storage array, comprising:

at least one processor;

a memory having at least a global portion thereof that is accessible by other directors of the storage array, wherein the global portion includes metadata having information that correlates logical device data with physical device data;

a interconnect fabric interface, wherein memory accesses for the global portion of the memory of the director are provided to the director through the interconnect fabric interface, wherein the director handles I/O operations based on the metadata stored in the global portion of the memory of the director, the metadata corresponding to the I/O operations, and wherein the director handles the I/O operations using the metadata stored in the global portion of the memory; and

a mechanism that, for a particular I/O operation, determines a corresponding director of the storage array to handle the particular I/O operation, wherein the corresponding director of the storage array is determined according to metadata that is provided in a portion of global memory provided on the corresponding director, wherein the metadata provided on the corresponding director corresponds to the I/O operation, and wherein the mechanism transfers a handling request for the particular I/O operation to the corresponding director.

16. A director, according to claim 15, wherein the physical device data is provided by at least one disk drive coupled to at least one of:

the director and the other directors.

17. A director, according to claim 15, wherein the memory includes a portion that is accessed exclusively by the at least one processor.

18. A director, according to claim 15, wherein the metadata stored on the director and the metadata provided on the corresponding director include device tables and cache slots.

19. A director, according to claim 15, wherein the interconnect fabric interface accesses an Internet Protocol (IP) network.

20. A director, according to claim 15, wherein memory accesses are performed using Direct Memory Access (DMA).