Recovery while programming non-volatile memory (NVM)

• US 7,945,825 B2
• Filed: 11/25/2008
• Issued: 05/17/2011
• Est. Priority Date: 11/25/2007
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Inventors: Tirosh, Ori, Cohen, Itzic, Hadas, Shmulik, Danon, Kobi
• Primary Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US12/323,333
• Publication Number:
  US 20090228739A1
• Time in Patent Office: 903 Days
• Field of Search: 714/721
• US Class Current: 714/721
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

Disclosed are methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) loading an SRAM with user data; (3) if programming is successful, then flipping bits in the SRAM; and (4) if programming is not successful, reading data back from the array to the SRAM.

Claims

1. A method of programming a set of erased non-volatile memory (NVM) cells comprising:

loading data to be programmed to the NVM cells onto a first set of Static Random Memory (SRAM) bits, wherein each of one or more SRAM bits corresponds to an NVM cell;

flipping each of the one or more SRAM bits corresponding to a given NVM cell once the given NVM cell has been program verified;

copying data back from each of the program verified NVM cells to respective corresponding one or more SRAM bits of the first set in the event an NVM cell cannot be program verified, wherein copying data back includes reading the NVM cells using a first read reference level; and

performing error detection on the bits of the SRAM once copying has been completed.

2. The method according to claim 1, further comprising, prior to copying data back from each of the program verified NVM cells to respective corresponding one or more SRAM bits, copying data from the first SRAM to a second SRAM.

3. The method according to claim 2, wherein upon detection of an error on the first SRAM occurring:

(1) copying data from the second SRAM set back to the first SRAM set, and (2) copying data back from each of the program verified NVM cells to respective corresponding one or more SRAM bits of the first set using a second read reference level.

4. The method according to claim 2, wherein copying data from the first set of SRAM to the second set of SRAM includes copying the error detection bits.

5. The method according to claim 2, wherein at least one of the SRAM sets is used for cache programming.

6. The method of claim 2, wherein the second set of SRAM cells is smaller than the first set.

7. A non-volatile memory (NVM) device comprising:

a set of non-volatile memory (NVM) cells;

control logic adapted to;

(1) load data to be programmed to the NVM cells onto a first set of Static Random Memory (SRAM) bits, wherein each of one or more SRAM bits corresponds to an NVM cell;

(2) flip each of the one or more SRAM bits corresponding to a given NVM cell once the given NVM cell has been program verified;

(3) copy data back from each of the program verified NVM cells to respective corresponding one or more SRAM bits of the first set in the event an NVM cell cannot be program verified, wherein copying data back includes reading the NVM cells using a first read reference level; and

(4) performing error detection on the bits of the SRAM once copying has been completed.

8. The device according to claim 7, wherein said control logic if further adapted to, prior to copying data back from each of the program verified NVM cells to respective corresponding one or more SRAM bits, copy data from the first SRAM to a second SRAM.

9. The device according to claim 8, wherein said control logic is further adapted to, upon detection of an error on the first SRAM occurring:

(1) copy data from the second SRAM set back to the first SRAM set, and (2) copy data back from each of the program verified NVM cells to respective corresponding one or more SRAM bits of the first set using a second read reference level.

10. The device according to claim 8, wherein said control logic is adapted to copy data from the first set of SRAM to the second set of SRAM including the error detection bits.

11. The device according to claim 8, wherein at least one of the SRAM sets is used for cache programming.

12. The device according to claim 8, wherein the second set of SRAM cells is smaller than the first set.