Pin-type chip tooling

• US 7,946,331 B2
• Filed: 01/10/2006
• Issued: 05/24/2011
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John, Frushour, Ross
• Primary Examiner(s): SELLS, JAMES D
• Application Number:
  US11/329,883
• Publication Number:
  US 20070120241A1
• Time in Patent Office: 1,960 Days
• Field of Search: 156/344, 156/538, 156/539, 156/580, 156/584, 156/581, 156/583.1, 156/583.3, 269/265, 269/266
• US Class Current: 156/581
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13084 : Four-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1358 : being stacked
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/45111 : Tin (Sn) as principal constituent
• CPC Class Codes: H01L 2224/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81054 : Composition of the atmosphere
• CPC Class Codes: H01L 2224/81136 : involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/81825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/81894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01S 2301/176 : Specific passivation layers on surfaces other than the emission facet
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0237 : by soldering
• CPC Class Codes: H01S 5/0422 : with n- and p-contacts on the same side of the active layer
• CPC Class Codes: H01S 5/0425 : Electrodes, e.g. characterised by the structure
• CPC Class Codes: H01S 5/04254 : characterised by the shape
• CPC Class Codes: H01S 5/04257 : having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/183 : having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
• CPC Class Codes: H01S 5/18308 : having a special structure for lateral current or light confinement

Abstract

An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when constrained, will allow a uniform vertical force to be applied to the chips.

Claims

1. An apparatus for bonding multiple chips with an element, the apparatus comprising:

a plurality of posts; and

a frame configured to releasably constrain the plurality of posts, wherein the frame is substantially orthogonal to the plurality of posts and the plurality of posts are configured to pass through the frame;

wherein at least some of the plurality of posts are configured to contact top surfaces of the multiple chips when unconstrained by the frame despite variations in heights of the multiple chips;

wherein the apparatus is configured to constrain the plurality of posts relative to the frame and apply a substantially uniform force to the multiple chips that is appropriate for bonding the multiple chips to the element; and

wherein the plurality of posts are configured to pass through the frame along an axis that is substantially orthogonal to the frame, and wherein the at least some of the plurality of posts are further configured to tilt away from the axis.

2. The apparatus of claim 1, wherein the at least some of the plurality of posts individually engage the multiple chips so that no two posts engage a common chip at the same time.

3. The apparatus of claim 2, wherein each of the plurality of posts has a face configured to engage at least a portion of one of the multiple chips, and wherein at least some of the plurality of posts have a circular cross-section near their respective faces.

4. The apparatus of claim 2, wherein each of the plurality of posts has a face configured to engage at least a portion of one of the multiple chips, and wherein at least some of the plurality of posts have a non-circular cross-section near their respective faces.

5. The apparatus of claim 1, wherein the at least some of the plurality of posts each have a substantially planar face configured to come into contact with one of the multiple chips.

6. The apparatus of claim 1, wherein the frame is further configured to receive the applied force, and wherein the constrained posts are further configured to transfer the applied force from the frame to the multiple chips.

7. The apparatus of claim 1, wherein a perimeter of one chip at a surface that is configured to contact a corresponding post defines a first area, wherein a perimeter of the corresponding post at a corresponding face defines a second area, and wherein the second area is at least as large as the first area.

8. The apparatus of claim 1, wherein at least one of the plurality of posts has a face that is complementary to a face of its corresponding chip.

9. The apparatus of claim 1, wherein at least one of the posts is configured to allow for application of a vacuum to its corresponding chip.

10. The apparatus of claim 2, wherein a perimeter of one chip at a surface that is configured to contact a corresponding post defines a first area, wherein a perimeter of the corresponding post at a corresponding face defines a second area, and wherein the second area is different from the first area.

11. The apparatus of claim 10, wherein at least one of the posts is configured to allow for application of a vacuum to the surface of the corresponding chip.

12. The apparatus of claim 1, wherein a subset of the plurality of posts is configured to collectively engage a surface of one of the multiple chips.

13. The apparatus of claim 12, wherein at least one of the posts in the subset has a circular cross-section near its face that is configured to engage the surface of one of the multiple chips.

14. The apparatus of claim 12, wherein at least one of the posts in the subset has a non-circular cross-section near its face that is configured to engage the surface of one of the multiple chips.

15. The apparatus of claim 12, wherein the face of each post in the subset is substantially planar.

16. The apparatus of claim 12, wherein the posts in the subset are configured to allow for application of a vacuum to the surface of the one of the multiple chips.

17. The apparatus of claim 12, wherein the frame is further configured to receive the applied force, and wherein the subset is further configured to transfer the applied force from the frame to the surface of the one of the multiple chips.

18. The apparatus of claim 12, wherein the subset of the plurality of posts is further configured to substantially enclose an end portion of the one of the multiple chips.

19. The apparatus of claim 18, wherein the subset of the plurality of posts, when constrained, is configured to constrain a lateral motion of the one of the multiple chips.

20. The apparatus of claim 9, wherein the at least one of the posts has a passageway for applying the vacuum to the corresponding chip.

21. The apparatus of claim 1, wherein the at least some of the plurality of posts are further configured to conform to topography of the multiple chips by substantially enclosing a chip with at least two posts or by having a post with a face that is complementary to a surface of the corresponding chip.

22. A system for bonding multiple chips having bonding surfaces to an element having a bonding surface, the system comprising:

multiple chips having a plurality of bonding surfaces;

an element having a second bonding surface; and

a bonding apparatus including;

a plurality of posts; and

a frame configured to releasably constrain the plurality of posts, wherein the frame is substantially orthogonal to the plurality of posts, and wherein the plurality of posts are configured to pass through the frame;

wherein at least some of the multiple chips have different heights;

wherein at least some of the plurality of posts conform to the different heights and are configured to contact the multiple chips;

wherein the at least some of the plurality of posts, when constrained by the frame, are configured to apply a substantially uniform force to the multiple chips to bring the plurality of bonding surfaces of the multiple chips into contact with the second bonding surface of the element; and

wherein the plurality of posts are configured to pass through the frame along an axis that is substantially orthogonal to the frame, and wherein the at least some of the plurality of posts are further configured to tilt away from the axis.

23. The system of claim 22, wherein at least one of the multiple chips engages a subset of the plurality of posts, and wherein the subset of the plurality of posts substantially encloses an end portion of the at least one of the multiple chips thereby substantially constraining a lateral motion of the at least one of the multiple chips.

24. The system of claim 22, wherein the plurality of posts further comprises a subset of posts configured to conform to and contact a first chip from the multiple chips.

25. The system of claim 24, wherein the subset of posts is further configured to substantially enclose an end portion of the first chip.

26. The system of claim 22, wherein a perimeter of a first chip from the multiple chips is configured to contact a corresponding post and define a first area, wherein a perimeter of the corresponding post at a corresponding face defines a second area, and wherein the second area is at least as large as the first area.