Power MOS transistor device and layout

• US 7,948,032 B2
• Filed: 05/19/2008
• Issued: 05/24/2011
• Est. Priority Date: 01/30/2008
• Status: Expired due to Fees

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Lee, Hsin-Ming, Chang, Chih-Heng
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Budd; Paul A
• Application Number:
  US12/122,722
• Publication Number:
  US 20090189220A1
• Time in Patent Office: 1,100 Days
• Field of Search: 257/E29.256, 257/341
• US Class Current: 257/341
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A power metal-oxide semiconductor (MOS) transistor device is provided. The power MOS transistor device includes a drain region disposed in a substrate, a gate structure layer disposed over the substrate, and enclosing a periphery of the drain region, and a source region formed in the substrate and distributed at an outer periphery of the gate structure layer. In addition, the MOS transistor device can, for example, form a transistor array.

Claims

1. A power metal-oxide semiconductor (MOS) transistor device, comprising:

four drain regions, disposed in a substrate;

a gate structure layer, disposed on the substrate, and enclosing a periphery of each of the drain regions, wherein the gate structure layer comprises;

four peripheral regions, respectively enclosing the four drain regions; and

one center region, located between the four peripheral regions, wherein the center region is a quadrangle having four corners to directly connect to the four peripheral regions; and

a source region, disposed in the substrate, and distributed at an outer periphery of the gate structure layer, wherein the source region continuously or discontinuously encloses the gate structure layer, and the center region of the gate structure layer has no portion of the source region.

2. The power MOS transistor device as claimed in claim 1, wherein the gate structure layer includes a stacked gate dielectric layer and a gate layer.

3. The power MOS transistor device as claimed in claim 1 further comprising a base region disposed adjacent to the source region and located at a periphery of the source region.

4. The power MOS transistor device as claimed in claim 3, wherein the base region is shared by an adjacent power MOS device.