MEMS package that includes MEMS device wafer bonded to cap wafer and exposed array pads

• US 7,948,043 B2
• Filed: 09/22/2009
• Issued: 05/24/2011
• Est. Priority Date: 06/14/2006
• Status: Expired due to Fees

• Current Assignee: Atria Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Pyo, Sung-Gyu, Kim, Dong-Joon
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US12/564,139
• Publication Number:
  US 20100006959A1
• Time in Patent Office: 609 Days
• Field of Search: 438/51
• US Class Current: 257/415
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

Claims

1. A package of a micro-electro-mechanical systems (MEMS) device, the package comprising:

a cap wafer;

a plurality of bonding bumps formed over the cap wafer;

a plurality of array pads arrayed on an outer side of the bonding bumps;

a sealing line formed between the bonding bumps and the array pads to encompass the bonding bumps; and

an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads,

wherein the MEMS device wafer comprises;

a silicon on insulator (SOI) substrate;

an insulation layer formed over the SOI substrate;

a plurality of inner pads formed over the insulation layer;

a plurality of barrier walls separated from the inner pads and bonded to the sealing line; and

a moving part supported by the inner pads.

2. The package of claim 1, wherein the bonding bumps and the sealing line are formed substantially at the same layer level.

3. The package of claim 1, wherein the cap wafer comprises:

a plurality of inner pads;

a plurality of outer pads;

a plurality of inner interconnection lines respectively coupling the inner pads to the outer pads;

an insulation layer covering the inner pads, the outer pads, and the inner interconnection lines;

a plurality of first plugs formed in the insulation layer and respectively coupling the inner pads to the bonding bumps; and

a plurality of second plugs formed in the insulation layer and respectively coupling the outer pads to the array pads.

4. The package of claim 3, wherein the inner pads, the outer pads, and the inner interconnection lines are formed substantially at the same layer level.

5. The package of claim 3, wherein the first plugs and the second plugs are formed substantially at the same layer level.

6. The package of claim 1, wherein the inner pads are bonded to respective ones of the bonding bumps.

7. The package of claim 1, wherein the moving part is formed between the barrier walls.

8. The package of claim 1, wherein the inner pads, the barrier walls, and the moving part each include substantially the same material.

9. The package of claim 8, wherein the inner pads, the barrier walls, and the moving part each include a silicon-based material.

10. The package of claim 1, wherein the cap wafer and the MEMS device wafer are separated to a certain distance by the sealing line and the barrier walls.

11. The package of claim 1, wherein the inner pads are bonded to respective ones of the bonding bumps through a bonding promoter.

12. The package of claim 11, wherein the bonding promoter includes one selected from a TiW/Au structure, a Ti/Al structure, a Ti/TiN/Al structure, and a TiN/Al structure.

13. The package of claim 1, wherein the barrier walls are bonded to the sealing line through a bonding promoter.

14. The package of claim 13, wherein the bonding promoter includes one selected from a TiW/Au structure, a Ti/Al structure, a Ti/TiN/Al structure, and a TiN/Al structure.

15. The package of claim 1, wherein the bonding bumps are formed to have substantially the same height as the sealing line.

16. The package of claim 15, wherein the bonding bumps are formed thicker than the array pads.

17. The package of claim 1, wherein the bonding bumps and the sealing line are formed with an area being about 7% to 35% of the total area of the cap wafer.