Semiconductor package and method of making the same

• US 7,948,095 B2
• Filed: 02/11/2009
• Issued: 05/24/2011
• Est. Priority Date: 02/12/2008
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: United Test and Assembly Center Limited (UTAC Holdings Ltd.)
• Inventors: Ng, Catherine Bee Liang, Sun, Anthony Yi-Sheng, Toh, Chin Hock
• Primary Examiner(s): Parekh; Nitin
• Application Number:
  US12/369,429
• Publication Number:
  US 20090200662A1
• Time in Patent Office: 832 Days
• Field of Search: 257/787, 257/774, 257/777, 257/686, 257/E23.145
• US Class Current: 257/790
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.

Claims

1. A semiconductor package comprising:

a substrate;

a first die having a front side, a back side, and a plurality of through silicon interconnects, the first die being stacked onto the substrate; and

a second die having a front side, a back side, and a first plurality of conductive bumps formed at the back side of the second die, the second die being stacked onto the first die and having under-filled the first plurality of conductive bumps such that the first plurality of conductive bumps electrically communicate with the through silicon interconnects;

wherein a first mold material encapsulates the second die and the front side of the first die; and

a second mold material encapsulates the first die, the second die, and a plurality of solder interconnects.

2. The semiconductor package of claim 1, wherein each of the through silicon interconnects further comprises:

an end portion at the back side of the first die and a top portion at the front side of the first die;

a dielectric layer formed along internal walls of the through silicon interconnect;

a barrier metal layer formed over the dielectric layer;

a seed layer formed over the barrier metal layer; and

a metallic material filling space within the internal walls of the through silicon interconnect.

3. The semiconductor package of claim 2, further comprising:

a metallic layer and a passivation layer formed on the front side of the first die so as to be non-overlapping;

a metallic layer and a passivation layer formed on the back side of the first die so as to be non-overlapping;

a plurality of under bump metallization (UBM) pads formed on the metallic layer on the back side of the first die; and

a second plurality of conductive bumps formed on the UBM pads.