Pixel having an organic light emitting diode and method of fabricating the pixel

• US 7,948,170 B2
• Filed: 02/24/2004
• Issued: 05/24/2011
• Est. Priority Date: 02/24/2003
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Tao, Sheng, Striakhilev, Denis, Vygranenko, Yuri, Nathan, Arokia
• Primary Examiner(s): Won; Bumsuk
• Application Number:
  US10/546,695
• Publication Number:
  US 20070029545A1
• Time in Patent Office: 2,646 Days
• Field of Search: 313498-512
• US Class Current: 313/506
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 50/828 Transparent cathodes, e.g. comprising thin metal layers
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planarization dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap.

Claims

1. A pixel having a vertical architecture in which a thin film transistor (TFT)-based backplane and an organic light emitting device (OLED) are formed on the same substrate, said pixel comprising:

a substrate having a substantially flat upper surface;

a TFT-based backplane formed on said substantially flat upper surface of said substrate for electrically driving the OLED, said TFT-based backplane having a vertical profile facing away from said upper surface of said substrate;

a planarization dielectric layer formed on top of said TFT based backplane and having a smooth, planarized upper surface for planarizing said vertical profile on the TFT based backplane;

the OLED formed on top of said planarized surface of said planarization dielectric layer, said OLED device having a bottom electrode, a top electrode, and the organic light emitting layer between the bottom and top electrodes, said bottom electrode being formed on said planarized surface, said top electrode being transparent so that light to be emitted by said OLED travels in a direction opposite to said substrate to form a top-emitting OLED;

the OLED being vertically integrated with the TFT based backplane via the planarization dielectric layer, the portion of the organic light emitting layer between the bottom and top electrodes of the OLED at least partially overlapping a gate, source, or drain node of a transistor of the TFT based backplane;

a first via in the planarization dielectric layer, for providing a communication path between the TFT based backplane and the OLED, wherein a sidewall of the first via is sloped against the TFT based backplane; and

an additional dielectric layer deposited on top of said bottom electrode for covering at least one of said first via and edges of said bottom electrode while leaving the rest of said bottom electrode uncovered, said organic light emitting layer being applied over said dielectric cap.

2. The pixel as claimed in claim 1,

wherein the additional dielectric layer provided between the OLED bottom electrode and one or more layers of the OLED device is patterned in such a way that it insulates the OLED layers from the OLED bottom electrode at pixel edges while leaving the rest of the OLED bottom electrode in the direct contact with the OLED layers.

3. The pixel as claimed in claim 1, wherein the pixel has a roughness of the order of 1 nm on the planarization dielectric layer and subsequent electrode layer.

4. The pixel as claimed in claim 3, wherein the planarization dielectric layer and the bottom electrode have a roughness of the order of 1 nm.

5. The pixel as claimed in claim 1, further comprising continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer.

6. The pixel as claimed in claim 1, further comprising a shield electrode formed over the TFT and at least over an area between the source and drain nodes of the TFT.

7. The pixel as claimed in claim 1, wherein the TFT based backplane includes:

a substrate;

gate, source and drain nodes;

an interlayer dielectric layer on the source and drain nodes; and

an interconnection plate patterned on a second via of the interlayer dielectric layer and being connected to the source or drain node, the first via being formed on the interconnection plate to provide the communication path through the interconnection plate.

8. The pixel as claimed in claim 7, further comprising:

a shield electrode disposed between the planarization dielectric layer and the interlayer dielectric layer and at least over an area between the source node and the drain node.

9. The pixel as claimed in claim 1, wherein the TFT based backplane comprises:

a substrate;

gate, source and drain nodes;

an interlayer dielectric layer on the source and drain nodes;

an interconnection plate patterned on a second via of the interlayer dielectric layer and contacting to the source or drain node; and

a contact plate on the interlayer dielectric layer and contacting the interconnection plate, the first via being formed on the contact plate to provide the communication path through the contact plate and the interconnection plate.

10. The pixel as claimed in claim 1, wherein the TFT based backplane includes:

a substrate;

gate, source and drain nodes; and

a contact plate, the source or drain material partially overlapping the contact plate, the first via being formed on the contact plate to provide the communication path through the contact plate.

11. The pixel as claimed in claim 10, further comprising:

a shield electrode is formed at least over an area between the source node and the drain node.

12. The pixel as claimed in claim 1, wherein the planarization dielectric layer includes photosensitive benzocylobutene (BCB), the slope of the first via being adjusted by the exposure time of the photosensitive BCB.

13. The pixel as claimed in claim 1, wherein the additional dielectric layer includes polymer dielectric, inorganic insulator, BCB, polyimide, polymer dielectric, silicon nitride, a thin film inorganic, or a combination thereof.

14. The pixel as claimed in claim 1, wherein the additional dielectric layer includes polymer dielectric, inorganic insulator, BCB, polyimide, polymer dielectric, silicon nitride, a thin film inorganic, or a combination thereof.

15. The pixel as claimed in claim 1, wherein the planalization dielectric layer comprises non-photosensitive benzocylobutene (BCB).

16. The pixel according to claim 1, wherein the pixel is a top emission pixel.

17. The pixel as claimed in claim 1, wherein the vertical profile of structures on the TFT based backplane has a sidewall angle not greater than 45 degrees.

18. A method of fabricating a display that includes multiple pixels each of which has a vertical architecture in which a thin film transistor (TFT)-based backplane and an organic light emitting device (OLED) are formed on the same substrate, the method comprising:

forming a TFT based backplane including a gate, source, and drain nodes on a substrate having a substantially flat upper surface, the TFT-based backplane having a vertical profile facing away from the upper surface of the substrate;

forming a planarization dielectric layer on top of said TFT based backplane, the planarization layer having a smooth, planarized upper surface for planarizing the vertical profile on the TFT based backplane;

forming a first via in the planarization dielectric layer, such that a sidewall of the first via is sloped against the TFT based backplane;

forming the OLED on top of the planarized surface of the planarization layer, the OLED having a top electrode and a bottom electrode and an organic light emitting layer between the top and bottom electrodes, the bottom electrode being formed on the planarized surface, the OLED being vertically integrated with the TFT-based backplane via the planarization layer, the portion of the organic light emitting layer between the top and bottom electrodes at least partially overlapping a gate, source, or drain node of the TFT based backplane, and the first via provides a communication path between the TFT backplane and the OLED, the top electrode being transparent so that light to be emitted by the OLED travels in a direction opposite to the substrate to form a top-emitting OLED; and

forming an additional dielectric layer for covering at least one of the first via and edges of the bottom electrode while leaving the rest of the bottom electrode uncovered.

19. A method as claimed in claim 18,

wherein the additional dielectric layer is formed between the OLED bottom electrode and one or more layers of the OLED device, such that the additional dielectric layer insulates the OLED layers from the OLED bottom electrode at pixel edges while leaving the rest of the OLED bottom electrode in the direct contact with the OLED layers.

20. A method as claimed in claim 18, further comprising:

applying the organic light emitting layer over the additional dielectric layer, the additional dielectric layer being a dielectric cap.

21. A method as claimed in claim 18, wherein the planarization dielectric layer comprises photosensitive benzocylobutene (BCB), the forming the first via comprising:

adjusting the exposure time of the photosensitive BCB to adjust the angle of the sidewall of the via against the TFT based backplane.

22. A method as claimed in claim 18, wherein the planarization dielectric layer comprises non-photosensitive benzocylobutene (BCB).

23. A method as claimed in claim 18, wherein the pixel is formed such that the pixel has a roughness of the order of 1 nm on the planarization dielectric layer and subsequent electrode layer.

24. A method as claimed in claim 18, further comprising providing continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer.

25. A method as claimed in claim 18, further comprising:

forming a shield electrode at least over an area between source and drain nodes of the TFT.

27. A method as claimed in claim 18, wherein the forming a TFT based backplane comprises:

patterning an interlayer dielectric on the TFT;

forming an interconnection plate on a second via of the interlayer dielectric layer, the interconnection plate being connected to the source or drain node; and

forming a contact plate on the interlayer dielectric layer so that the contact plate contacts the interconnection plate, the first via being formed on the contact plate to provide the communication path through the contact plate and the interconnection plate.

28. A method as claimed in claim 18, wherein the forming a TFT based backplane comprises:

forming a contact plate and a source or drain so that the source or drain partially overlaps the contact plate, the first via being formed on the contact plate to provide the communication path through the contact plate.

29. A method according to claim 18, wherein the pixel is a top emission pixel.

26. A method as claimed in 18, wherein the forming a TFT based backplane comprises:

patterning an interlayer dielectric on the TFT; and

patterning an interconnection plate on a second via of the interlayer dielectric layer, the interconnection plate being connected to the source or drain node, the first via being formed on the interconnection plate to provide the communication path through the interconnection plate.