Method and apparatus for buffering signals in voltage domains
First Claim
1. An integrated circuit comprising:
- a switch operatively coupled to a selectably on voltage supply grid, the switch having a first node and a second node and operative to selectively turn on and off the selectably on voltage supply grid, the selectably on voltage supply grid operatively coupled to a positive voltage supply grid; and
a buffer cell cluster operatively coupled to the selectably on voltage supply grid,wherein the buffer cell cluster comprises at least one initial buffer cell and a pair of insulator cells and is operatively coupled to the positive voltage supply grid, and wherein the at least one initial buffer cell is operative to buffer a feed-through signal having an activation voltage level defined substantially at the voltage level of the positive voltage supply grid.
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Accused Products
Abstract
An integrated circuit includes first and second voltage domains. The first voltage domain is associated with a positive voltage supply grid and the second voltage domain is associated with a selectably on voltage supply grid. A switch is used to selectably switch on and off the selectably on voltage supply grid to power the second voltage domain. A buffer cell cluster of at least on initial buffer cell and a pair of insulator cells is coupled to the positive voltage supply grid electrically independent of the nodes of a switch and is capable of buffering a feed-through signal having a logic one voltage level defined substantially at the voltage level of the positive voltage supply grid. The buffer cell cluster has two distal ends. buffer cell cluster, at one distal end, is coupled to a first insulator cell of the pair of cells while, at the other distal end, the buffer cell cluster is coupled to a second insulator cell of the pair of the cells.
19 Citations
25 Claims
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1. An integrated circuit comprising:
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a switch operatively coupled to a selectably on voltage supply grid, the switch having a first node and a second node and operative to selectively turn on and off the selectably on voltage supply grid, the selectably on voltage supply grid operatively coupled to a positive voltage supply grid; and a buffer cell cluster operatively coupled to the selectably on voltage supply grid, wherein the buffer cell cluster comprises at least one initial buffer cell and a pair of insulator cells and is operatively coupled to the positive voltage supply grid, and wherein the at least one initial buffer cell is operative to buffer a feed-through signal having an activation voltage level defined substantially at the voltage level of the positive voltage supply grid. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit comprising:
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a third voltage domain associated with a positive voltage supply grid; a switch operatively coupled to a selectably on voltage supply grid, the switch having a first node and a second node and operative to selectively turn on and off the selectably on voltage supply grid; a plurality of standard cells associated with a first voltage domain and operatively powered by the positive voltage supply grid, wherein the plurality of standard cells includes a plurality of transmitting standard cells each operative to generate a corresponding feed-through signal having an activation voltage level defined substantially at the voltage level of the positive voltage supply grid; a buffer cell cluster comprising at least one initial cell and a pair of insulator cells, wherein the buffer cell cluster is coupled to the positive voltage supply grid, and wherein the at least one initial buffer cell is operative to buffer at least one feed-through signal generated by the plurality of transmitting standard cells; a plurality of standard cells associated with the second voltage domain operatively powered by the selectably on voltage supply grid; and a plurality of standard cells associated with the third voltage domain and operatively powered by the positive voltage supply grid, wherein the plurality of standard cells includes a plurality of receiving standard cells each operative to receive one buffered feed-through signal. - View Dependent Claims (14)
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15. Memory comprising executable instructions capable of being executed by one or more processors such that, when the executable instructions are executed by the one or more processors, the executable instructions cause the one or more processors to:
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provide an integrated circuit layout; and store the integrated circuit layout in one of;
the memory and other memory capable of being accessed by the one or more processors,wherein the integrated circuit layout is capable of being used to fabricate an integrated circuit that comprises; a switch operatively coupled to a selectably on voltage supply grid, the switch having a first node and a second node and operative to selectively turn on and off the selectably on voltage supply grid, the selectably on voltage supply grid operatively coupled to a positive voltage supply grid; and a buffer cell cluster operatively coupled to the selectably on voltage supply grid, wherein the buffer cell cluster comprises at least one initial buffer cell and a pair of insulator cells and is operatively coupled to the positive voltage supply grid, and wherein the at least one initial buffer cell is operative to buffer a feed-through signal having an activation voltage level defined substantially at the voltage level of the positive voltage supply grid. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification