Mixed multi-level cell and single level cell storage device

• US 7,948,798 B1
• Filed: 07/22/2009
• Issued: 05/24/2011
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sheredy, Joseph, Nguyen, Lau
• Primary Examiner(s): Lam; David
• Application Number:
  US12/507,548
• Time in Patent Office: 671 Days
• Field of Search: 365/185.11, 365/185.29, 365/185.18, 365/185.03, 365/185.33
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Claims

1. A method of programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising:

assigning a weighting factor to each memory block of the plurality of memory blocks, the weighting factor being assigned to each memory block based at least in part on whether the memory block is an SLC memory block or an MLC memory block;

tracking a number of write-erase cycles for each memory block of the plurality of memory blocks; and

selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks.

2. The method of claim 1, wherein selecting one or more memory blocks for writing data further comprises:

determining a weighted number of write-erase cycles for each memory block of the plurality of memory blocks, wherein the weighted number of write-erase cycles for each memory block is a function of a corresponding tracked number of write-erase cycles and corresponding weighting factor; and

selecting one or more memory blocks based at least in part on the determined weighted number of write-erase cycles.

3. The method of claim 2, wherein determining the weighted number of write-erase cycles further comprises:

determining the weighted number of write-erase cycles for each memory block by multiplying the tracked number of write-erase cycles with the assigned weighting factor for the memory block.

4. The method of claim 1, wherein assigning the weighting factor further comprises:

assigning a first weighting factor to each SLC memory block; and

assigning a second weighting factor to each MLC memory block.

5. The method of claim 4, wherein the first weighting factor is larger than the second weighting factor.

6. The method of claim 4, wherein the ratio of the first weighting factor and the second weighting factor is substantially proportional to a ratio of average number of write-erase cycles an average MLC memory cell and an average SLC memory cell withstands.

7. The method of claim 1, wherein each SLC memory block includes one or more SLC memory cells, and each MLC memory block includes one or more MLC memory cells.

8. A memory system comprising:

a flash memory device comprising a plurality of memory blocks, wherein each memory block of plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block; and

a memory controller configured to;

assign a weighting factor to each memory block of the plurality of memory blocks, the weighting factor being assigned to each memory block based at least in part on whether the memory block is an SLC memory block or an MLC memory block;

track a number of write-erase cycles for each memory block of the plurality of memory blocks; and

select one or more memory blocks for writing data, based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks.

9. The memory system of claim 8, further comprising:

a wear-leveling table, wherein the memory controller is configured to update the wear-leveling table with the weighting factors and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks.

10. The memory system of claim 8, wherein the memory controller is further configured to:

assign a first weighting factor to each SLC memory block;

assign a second weighting factor to each MLC memory block;

determine a weighted number of write-erase cycles for each of the plurality of memory blocks, wherein the weighted number of write-erase cycles for each memory block is a function of a corresponding tracked number of write-erase cycles and a corresponding weighting factor; and

select either an SLC memory block or an MLC memory block for writing data based at least in part on the determined weighted number of write-erase cycles.

11. The memory system of claim 8, wherein each of the SLC memory blocks includes one or more SLC memory cells, and each of the plurality of MLC memory blocks includes one or more MLC memory cells.