Semiconductor memory device and reset control circuit of the same
First Claim
1. A semiconductor memory device comprising:
- a reset control circuit;
monitoring a state of a reset signal in synchronization with an enablement time point of the reset signal and outputting monitoring signals corresponding to a state of the reset signal,enabling and outputting a reset control signal, wherein the reset control signal is enabled when states of the monitoring signals are equal, andstopping the monitoring of the reset signal in synchronization with the enablement of the reset control signal; and
an internal circuit receiving the reset control signal, wherein an initialization of the internal circuit is controlled by the reset control signal.
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Abstract
The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the states of the monitoring signals are equal, and ends the monitoring of the reset signal in synchronization with the enablement of the reset control signal. An internal circuit receives the reset control signal, and the reset control signal controls the initialization of the internal circuit. When the reset signal maintains the enablement state for a predetermined period, the reset control signal is enabled, making it possible to prevent reset malfunction associated with a glitch occurring in the reset signal.
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Citations
25 Claims
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1. A semiconductor memory device comprising:
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a reset control circuit; monitoring a state of a reset signal in synchronization with an enablement time point of the reset signal and outputting monitoring signals corresponding to a state of the reset signal, enabling and outputting a reset control signal, wherein the reset control signal is enabled when states of the monitoring signals are equal, and stopping the monitoring of the reset signal in synchronization with the enablement of the reset control signal; and an internal circuit receiving the reset control signal, wherein an initialization of the internal circuit is controlled by the reset control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A reset control circuit of a semiconductor memory device comprising:
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an oscillator receiving a reset signal and generating an internal clock signal according to the reset signal; a reset signal monitor unit monitoring a state of the reset signal in synchronization with a toggling of the internal clock signal and outputting monitoring signals corresponding to the state of the reset signal; a reset control signal output unit outputting a reset control signal controlling an initialization of an internal circuit of the semiconductor memory device according to the monitoring signals; and a monitor initialization unit logically combining the reset signal and the reset control signal to output a monitor initialization signal for initializing the reset signal monitor unit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A reset control circuit of a semiconductor memory device comprising:
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a reset signal monitor unit receiving an external clock signal and a reset signal and monitoring a state of the reset signal in synchronization with the external clock signal and outputting monitoring signals corresponding to the state of the reset signal; a reset control signal output unit outputting the reset control signal controlling an initialization of an internal circuit of the semiconductor memory device according to the monitoring signals; and a monitor initialization unit logically combining the reset signal and the reset control signal to output a monitor initialization signal for initializing the reset signal monitor unit. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification