Implementation of decimation filter in integrated circuit device using ram-based data storage

• US 7,949,699 B1
• Filed: 08/30/2007
• Issued: 05/24/2011
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Neoh, Hong Shan, Esposito, Benjamin
• Primary Examiner(s): Malzahn; David H
• Application Number:
  US11/848,020
• Time in Patent Office: 1,363 Days
• Field of Search: None
• US Class Current: 708/313
• CPC Class Codes: H03H 17/0223 Computation saving measures; Accelerating measures computations per se G06F
• CPC Class Codes: H03H 17/0225 Measures concerning the multipliers
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H03H 2017/0298 DSP implementation
• CPC Class Codes: H03H 2218/085 Multipliers

Abstract

A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.

Claims

1. A FIR filter structure for operating in decimation filter mode;

said FIR filter structure comprising;

a first number of multipliers each corresponding to one or more taps of said FIR filter structure, each of said multipliers having first and second multiplicand inputs;

a second number of coefficient memories, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients; and

a fourth number of data sample memories, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples;

wherein;

all of said multipliers, said coefficient memories, and said data sample memories operate at a single clock rate.

2. The FIR filter structure of claim 1 wherein:

said FIR filter structure is implemented in an integrated circuit comprising at least one block of user-configurable random access memory; and

said coefficient memories and said data sample memories are implemented in said at least one block of user-configurable random access memory.

3. The FIR filter structure of claim 2 wherein said integrated circuit comprises a programmable logic device.

4. The FIR filter structure of claim 1 wherein:

said FIR filter structure operates in a non-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to one tap of said FIR filter structure;

said first number is equal to a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said length;

said fourth number is equal to said first number; and

said fifth number is equal to said decimation factor.

5. The FIR filter structure of claim 1 wherein:

said FIR filter structure operates in an even-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to two taps of said FIR filter structure;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

6. The FIR filter structure of claim 1 wherein:

said FIR filter structure operates in an odd-symmetric decimation filter mode having a length and a decimation factor;

said FIR filter structure further comprises a multiplexer between one of said data sample memories and one of said multipliers, whereby a zero input can be selected for said one of said multipliers;

each of said multipliers, except for said one of said multipliers, corresponds to two taps of said FIR filter structure, and said one of said multipliers corresponds to one tap of said FIR filter structure;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

7. An integrated circuit device configured as a FIR filter for operating in one of decimation filter mode, said integrated circuit device having a plurality of multipliers and at least one user-configurable block of random access memory and comprising:

a first number of multipliers each corresponding to one or more taps of said FIR filter, each of said multipliers having first and second multiplicand inputs;

a second number of coefficient memories configured from said at least one user-configurable block of random access memory, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients; and

a fourth number of data sample memories configured from said at least one user-configurable block of random access memory, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples;

wherein;

all of said multipliers, said coefficient memories, and said data sample memories operate at a single clock rate.

8. The integrated circuit device of claim 7 wherein:

said FIR filter operates in a non-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to one tap of said FIR filter;

said first number is equal to a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said length;

said fourth number is equal to said first number; and

said fifth number is equal to said decimation factor.

9. The integrated circuit device of claim 7 wherein:

said FIR filter operates in an even-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to two taps of said FIR filter;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

10. The integrated circuit device of claim 7 wherein:

said FIR filter operates in an odd-symmetric decimation filter mode having a length and a decimation factor;

said FIR filter further comprises a multiplexer between one of said data sample memories and one of said multipliers, whereby a zero input can be selected for said one of said multipliers;

each of said multipliers, except for said one of said multipliers, corresponds to two taps of said FIR filter, and said one of said multipliers corresponds to one tap of said FIR filter;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

11. The integrated circuit device of claim 7, wherein said integrated circuit device comprises a programmable logic device.

12. A method of programmably configuring an integrated circuit device as a FIR filter for operating in decimation filter mode, said integrated circuit device having a plurality of multipliers and at least one user-configurable block of random access memory, said method comprising:

programmably configuring a first number of multipliers to each correspond to one or more taps of said FIR filter, each of said multipliers having first and second multiplicand inputs;

programmably configuring a second number of coefficient memories from said at least one user-configurable block of random access memory, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients;

programmably configuring a fourth number of data sample memories from said at least one user-configurable block of random access memory, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples; and

programmably configuring data read patterns for reading said data samples and said coefficients from said at least one user-configurable random access memory in an order corresponding to shifting of said data samples and said coefficients through said FIR filter.

13. The method of claim 12 wherein:

said integrated circuit device is configured as a FIR filter that operates in a non-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to one tap of said FIR filter;

said first number is equal to a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said length;

said fourth number is equal to said first number; and

said fifth number is equal to said decimation factor.

14. The method of claim 12 wherein:

said integrated circuit device is configured as a FIR filter structure that operates in an even-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to two taps of said FIR filter;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

15. The method of claim 12 wherein:

said integrated circuit device is configured as a FIR filter that operates in an odd-symmetric decimation filter mode having a length and a decimation factor;

said method further comprises configuring a multiplexer between one of said data sample memories and one of said multipliers, whereby a zero input can be selected for said one of said multipliers;

each of said multipliers, except for said one of said multipliers, corresponds to two taps of said FIR filter, and said one of said multipliers corresponds to one tap of said FIR filter;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

16. A data storage medium encoded with machine-executable instructions for performing a method of programmably configuring an integrated circuit device as a FIR filter for operating in decimation filter mode, said integrated circuit device having a plurality of multipliers and at least one user-configurable block of random access memory, said method comprising:

programmably configuring a first number of multipliers to each correspond to one or more taps of said FIR filter, each of said multipliers having first and second multiplicand inputs;

programmably configuring a second number of coefficient memories from said at least one user-configurable block of random access memory, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients;

programmably configuring a fourth number of data sample memories from said at least one user-configurable block of random access memory, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples; and

programmably configuring data read patterns for reading said data samples and said coefficients from said at least one user-configurable random access memory in an order corresponding to shifting of said data samples and said coefficients through said FIR filter.

17. The data storage medium of claim 16 wherein said instructions for said programmably configuring said FIR filter comprise instructions for programmably configuring said FIR filter such that:

said integrated circuit device is configured as a FIR filter that operates in a non-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to one tap of said FIR filter;

said first number is equal to a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said length;

said fourth number is equal to said first number; and

said fifth number is equal to said decimation factor.

18. The data storage medium of claim 16 wherein said instructions for said programmably configuring said integrated circuit device as a FIR filter comprise instructions for programmably configuring said FIR filter such that:

said integrated circuit device is configured as a FIR filter that operates in an even-symmetric decimation filter mode having a length and a decimation factor;

each of said multipliers corresponds to two taps of said FIR filter;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.

19. The data storage medium of claim 16 wherein said instructions for said programmably configuring said integrated circuit device as a FIR filter comprise instructions for programmably configuring said FIR filter such that:

said integrated circuit device is configured as a FIR filter that operates in an odd-symmetric decimation filter mode having a length and a decimation factor;

said FIR filter further comprises a multiplexer between one of said data sample memories and one of said multipliers, whereby a zero input can be selected for said one of said multipliers;

each of said multipliers, except for said one of said multipliers, corresponds to two taps of said FIR filter, and said one of said multipliers corresponds to one tap of said FIR filter;

said first number is equal to one-half a quotient of said length and said decimation factor;

said second number is equal to said first number;

said third number is equal to said decimation factor;

said fourth number is equal to twice said first number; and

said fifth number is equal to said length.