Extended link monitoring channel for 10 Gb/s Ethernet

• US 7,949,782 B2
• Filed: 11/06/2003
• Issued: 05/24/2011
• Est. Priority Date: 11/06/2003
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wolski, Stanislas, Mathur, Niraj Rajendra, Trepanier, Daniel Pierre, Popescu, Petre
• Primary Examiner(s): Neurauter, Jr.; George C
• Assistant Examiner(s): Joshi; Suraj
• Application Number:
  US10/701,485
• Publication Number:
  US 20050102419A1
• Time in Patent Office: 2,756 Days
• Field of Search: 709/238
• US Class Current: 709/238
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0811 by checking connectivity

Abstract

The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Claims

1. A transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising:

a 10 Gigabit attachment unit interface (XAUI) for providing a connection between the transceiver and the Ethernet media access control (MAC) layer device;

a media dependent interface (MDI) for providing the 10 Gb/s Ethernet link to the transceiver; and

a physical coding sublayer (PCS) extension circuit for implementing an extended link monitoring channel for said link for communicating link related information during Inter Packet Gaps (IPG) between user data packets, the PCS extension circuit comprising a processor configured with processor-executable instructions to perform operations comprising;

initializing the extended link monitoring channel by determining Inter Packet Gaps (IPGs) between blocks of user data, substituting selected IPG with ping blocks that are control blocks to be sent to a far end such that only each (N₁+1)-th idle block is substituted with the ping block until a total of Nx ping blocks has been substituted, and receiving ping blocks from the far end such that at least N_R ping blocks are separated by no more than N_J idle blocks, N_R are less or equal to N_X, and N_J are equal to or greater than N_J, wherein N_J=16, N_X=16, N_R=8, N_J=32;

communicating link monitoring information over the extended link monitoring channel by determining Inter Packet Gaps (IPG) between blocks of user data, and substituting, for the extended link monitoring channel, selected Inter Packet Gaps (IPG) with extended link monitoring blocks including blocks to carry link related information and control blocks constructed using selected reserved codes of IEEE 802.3 Ethernet standard; and

splitting the extended link monitoring channel by multiplexing a number of virtual link monitoring channels over the same link at the physical layer, each of the virtual link monitoring channels intended for communicating a different type of the link related information.

2. The transceiver of claim 1, wherein the processor of the PCS extension circuit is configured with processor-executable instructions to perform operations further comprising:

processing a 10 Gb/s Ethernet signal in the form of 64B/66B blocks.

3. The transceiver of claim 2, wherein the processor of the PCS extension circuit is configured with processor-executable instructions to perform operations further comprising:

determining Inter Packet Gaps (IPG) within said Ethernet signal and replacing selected Inter Packet Gaps (IPG) with extended link monitoring blocks; and

determining extended link monitoring blocks within said Ethernet signal and replacing them with Inter Packet Gaps (IPG).

4. The transceiver of claim 3, wherein the PCS extension circuit is controlled by an external device to initialize the extended link monitoring channel, and to insert and extract the link related information.

5. The transceiver of claim 3, wherein the processor of the PCS extension circuit is further configured with processor-executable instructions to perform operations further comprising:

generating a pseudo-random bit sequence (PRBS) and evaluating a received PRBS to determine a bit error rate (BER) for the link.

6. The transceiver of claim 1, wherein the link is a 10GBASE-R Ethernet link of the IEEE 802.3 Ethernet standard.

7. The transceiver of claim 1, wherein the link is an optical link.

8. A physical coding sublayer (PCS) extension circuit for a 10 Gb/s Ethernet transceiver, providing signal adaptation between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, the PCS extension circuit comprising:

a first interface for connecting the PCS extension circuit to a PCS 64B/66B coder circuit;

a second interface for connecting the PCS extension circuit to a PCS scrambler circuit; and

a processor configured with processor-executable instructions to perform operations comprising;

initializing an extended link monitoring channel for the link by determining Inter Packet Gaps (IPGs) between blocks of user data, substituting selected IPG with ping blocks that are control blocks to be sent to a far end such that only each (N₁+1)-th idle block is substituted with the ping block until a total of Nx ping blocks has been substituted, and receiving ping blocks from the far end such that at least N_R ping blocks are separated by no more than N_J idle blocks, N_R are less or equal to N_X, and N_J are equal to or greater than N_J, wherein N_J=16, N_X=16, N_R=8, N_J=32;

communicating link monitoring information over the extended link monitoring channel by determining Inter Packet Gaps (IPG) between blocks of user data, and substituting, for the extended link monitoring channel, selected Inter Packet Gaps (IPG) with extended link monitoring blocks including blocks to carry link related information and control blocks constructed using selected reserved codes of IEEE 802.3 Ethernet standard; and

splitting the extended link monitoring channel by multiplexing a number of virtual link monitoring channels over the same link at the physical layer, each of the virtual link monitoring channels intended for communicating a different type of the link related information.

9. The PCS extension circuit of claim 8, wherein the processor is configured with processor-executable instructions to perform operations further comprising:

processing an Ethernet signal in the form of 64B/66B blocks.

10. The PCS extension circuit of claim 9, wherein the processor is configured with processor-executable instructions to perform operations further comprising:

determining idle blocks within the Ethernet signal and replacing selected idle blocks with extended link monitoring blocks; and

determining extended link monitoring blocks within said Ethernet signal and replacing them with idle blocks.

11. The PCS extension circuit of claim 10, wherein the processor is further configured with processor-executable instructions such that the PCS extension circuit is controlled by an external device to initialize the extended link monitoring channel, and to insert and extract the link related information.

12. The PCS extension circuit of claim 10, wherein the processor is further configured with processor-executable instructions to perform operations further comprising:

generating a pseudo-random bit sequence (PRBS); and

evaluating a received PRBS for to determine a bit error rate (BER) for the link.

13. The PCS extension circuit of claim 8, wherein the transceiver is designed for a 10GBASE-R Ethernet link of the IEEE 802.3 Ethernet standard.

14. The PCS extension circuit of claim 8, wherein the transceiver is designed for an optical link.

15. A link system in an a 10 Gb/s Ethernet network, comprising at least two nodes connected by a 10 Gb/s Ethernet link, the link system having a transceiver between an Ethernet media access control (MAC) layer device and the 10 Gb/s Ethernet link, the transceiver comprising:

a 10 Gigabit attachment unit interface (XAUI) for providing a connection between the transceiver and the Ethernet media access control (MAC) layer device;

a media dependent interface (MDI) for providing the 10 Gb/s Ethernet link to the transceiver; and

a physical coding sublayer (PCS) extension circuit for implementing an extended link monitoring channel for said link for transmitting link related information during Inter Packet Gaps (IPG) between user data packets, the PCS extension circuit comprising a processor configured with processor-executable instructions to perform operations comprising;

initializing the extended link monitoring channel by determining Inter Packet Gaps (IPGs) between blocks of user data, substituting selected IPG with ping blocks that are control blocks to be sent to a far end such that only each (N₁+1)-th idle block is substituted with the ping block until a total of Nx ping blocks has been substituted, and receiving ping blocks from the far end such that at least N_R ping blocks are separated by no more than N_J idle blocks, N_R are less or equal to N_X, and N_J are equal to or greater than N_J, wherein N_J=16, N_X=16, N_R=8, N_J=32;

communicating link monitoring information over the extended link monitoring channel by determining Inter Packet Gaps (IPG) between blocks of user data, and

substituting, for the extended link monitoring channel, selected Inter Packet Gaps (IPG) with extended link monitoring blocks including blocks to carry link related information and control blocks constructed using selected reserved codes of IEEE 802.3 Ethernet standard; and

splitting the extended link monitoring channel by multiplexing a number of virtual link monitoring channels over the same link at the physical layer, each of the virtual link monitoring channels intended for communicating a different type of the link related information.

16. The link system of claim 15, wherein the processor of the PCS extension circuit is configured with processor-executable instructions to perform operations further comprising:

processing an Ethernet signal in the form of 64B/66B blocks by determining idle blocks within the Ethernet signal and replacing selected idle blocks with extended link monitoring blocks; and

determining extended link monitoring blocks within the Ethernet signal and replacing them with idle blocks.

17. The link system of claim 16, wherein the processor of the PCS extension circuit is configured with processor-executable instructions to perform operations further comprising:

generating a pseudo-random bit sequence (PRBS) to be sent through said extended link monitoring channel, and

evaluating a received PRBS for the purpose of determining a bit error rate (BER) for the link.

18. A method for implementing an extended link monitoring channel for a 10 Gb/s Ethernet link carrying an Ethernet signal in the form of blocks of N bits, the method comprising:

initializing the extended link monitoring channel by determining Inter Packet Gaps (IPGs) between blocks of user data, substituting selected IPG with ping blocks that are control blocks to be sent to a far end such that only each (N₁+1)-th idle block is substituted with the ping block until a total of Nx ping blocks has been substituted, and receiving ping blocks from the far end such that at least N_R ping blocks are separated by no more than N_J idle blocks, N_R are less or equal and N_X, and N_J are equal to or great than N_J, wherein N_J=16, N_X=16, N_R=8, N_J=32;

communicating link monitoring information over the extended link monitoring channel by

determining Inter Packet Gaps (IPG) between blocks of user data, and

substituting, for the extended link monitoring channel, selected Inter Packet Gaps (IPG) with extended link monitoring blocks including blocks to carry link related information and control blocks constructed using selected reserved codes of IEEE 802.3 Ethernet standard; and

splitting the extended link monitoring channel by multiplexing a number of virtual link monitoring channels over the same link at the physical layer, each of the virtual link monitoring channels intended for communicating a different type of the link related information.

19. The method of claim 18, the method being performed for the Ethernet signal in the form of blocks of 66 bits according to the IEEE 802.3 Ethernet standard for 10GBASE-R Ethernet links.

20. The method of claim 18, wherein substituting selected IPG blocks with ping blocks comprises substituting with ping blocks constructed with such selected reserved codes of the IEEE 802.3 Ethernet standard that, when received by a transceiver at the far end which lacks the PCS extension circuit, the ping blocks will not be recognized and interpreted as if they were idle blocks of the standard.

21. The method of claim 18, wherein substituting selected IPG blocks with extended link monitoring blocks comprises substituting each of the selected IPG blocks with one of the following types of the extended link monitoring blocks:

a Q-start block;

a channel data block; and

a Q-stop block, wherein the Q-start block and Q-stop block are control blocks, and the channel data block carries the link related information.

22. The method of claim 21, wherein substituting the selected IPG blocks comprises substituting the selected IPG blocks with a sequence of the Q-start block, zero or more of the channel data blocks, and the Q-stop block, the sequence forming a link monitoring packet.

23. The method of claim 21, wherein substituting with the Q-start block comprises substituting with the Q-start block having an identifier for a virtual link monitoring channel within the extended link monitoring channel, the virtual link monitoring channel communicating a specific type of the link related information.

24. The method of claim 23, wherein the link related information is one or more of the following:

a pseudo random bit sequence (PRBS) for bit error rate measurement;

data from a digital optical monitoring (DOM) subsystem for monitoring optical link parameters;

information contained in registers of the PCS devices; and

link states and alarms.

25. A system for implementing an extended link monitoring channel for a 10 Gb/s Ethernet link carrying an Ethernet signal in the form of blocks of N bits, the system comprising:

means for initializing the extended link monitoring channel by determining Inter Packet Gaps (IPGs) between blocks of user data, substituting selected IPG with ping blocks that are control blocks to be sent to a far end such that only each (N₁+1)-th idle block is substituted with the ping block until a total of Nx ping blocks has been substituted, and receiving ping blocks from the far end such that at least N_R ping blocks are separated by no more than N_J idle blocks, N_R are less or equal to N_X, and N_J are equal to or greater than N_J, wherein N_J=16, N_X=16, N_R=8, N_J=32;

means for communicating link monitoring information over the extended link monitoring channel by determining Inter Packet Gaps (IPG) between blocks of user data, and substituting, for the extended link monitoring channel, selected Inter Packet Gaps (IPG) with extended link monitoring blocks including blocks to carry link related information and control blocks constructed using selected reserved codes of IEEE 802.3 Ethernet standard; and

means for splitting the extended link monitoring channel by multiplexing a number of virtual link monitoring channels over the same link at the physical layer, each of the virtual link monitoring channels intended for communicating a different type of the link related information.

26. The system of claim 25, further comprising:

means for processing the Ethernet signal in the form of blocks of 66 bits according to the IEEE 802.3 Ethernet standard for 10GBASE-R Ethernet links.

27. The system of claim 25, wherein means for initializing the extended link monitoring channel comprises means for substituting selected IPG blocks with ping blocks constructed with such selected reserved codes of the IEEE 802.3 Ethernet standard such that, when received by a transceiver at the far end which lacks the PCS extension circuit, the ping blocks will not be recognized and interpreted as if they were idle blocks of the standard.

28. The system of claim 25, wherein means for initializing the extended link monitoring channel comprises means for substituting each of the selected IPG blocks with one of the following types of the extended link monitoring blocks:

a Q-start block;

a channel data block; and

a Q-stop block, wherein the Q-start block and Q-stop block are control blocks, and the channel data block carries the link related information.

29. The system of claim 28, wherein means for substituting each of the selected IPG blocks comprises means for substituting the selected IPG blocks with a sequence of the Q-start block, zero or more of the channel data blocks, and the Q-stop block, such that the sequence forms a link monitoring packet.

30. The system of claim 28, wherein means for substituting each of the selected IPG blocks comprises means for substituting with a Q-start block having an identifier for a virtual link monitoring channel within the extended link monitoring channel, the virtual link monitoring channel communicating a specific type of the link related information.

31. The system of claim 25, wherein means for communicating link monitoring information comprises means communicating link related information that is one or more of the following:

a pseudo random bit sequence (PRBS) for bit error rate measurement;

data from a digital optical monitoring (DOM) subsystem for monitoring optical link parameters;

information contained in registers of the PCS devices; and

link states and alarms.