System and method for transmitting data packets in a computer system having a memory hub architecture

• US 7,949,803 B2
• Filed: 08/31/2009
• Issued: 05/24/2011
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joe, James, Ralph
• Primary Examiner(s): Tsai; Henry W
• Assistant Examiner(s): Nam; Hyun
• Application Number:
  US12/550,911
• Publication Number:
  US 20090319714A1
• Time in Patent Office: 631 Days
• Field of Search: 710/36, 711/149, 711/154, 711/105
• US Class Current: 710/36
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.

Claims

1. A memory hub, comprising:

an upstream transmission port configured to transmit a digital signal;

an upstream reception port configured to receive a digital signal;

a downstream transmission port configured to transmit a digital signal;

a downstream reception port configured to receive a digital signal;

a downstream request routing circuit coupled to the downstream reception port, the local memory port and the downstream transmission port, the downstream request routing circuit being configured to determine whether the memory request is directed to a local memory device or whether the memory request is directed to a downstream memory device, the downstream request routing circuit further being configured to couple the digital signal received by the downstream reception port to the local memory port responsive to a determination that the memory request is directed to a local memory device and to couple the digital signal received by the downstream reception port to the downstream transmission port responsive to a determination that the memory request is directed to a downstream memory device;

a bypass circuit coupled to a local memory port, the upstream transmission port and the upstream reception port, the bypass circuit being configured to selectively couple the upstream transmission port to the local memory port or to the upstream reception port; and

a breakpoint circuit coupled to the bypass circuit configured to identify a breakpoint in a digital signal received from either the local memory port or the upstream reception port, the breakpoint circuit being configured to be responsive to the identification to couple a control signal to the bypass circuit to initiate a switch between the upstream reception port and the local memory port.

2. The memory hub of claim 1, wherein the breakpoint circuit is configured to implement a switching algorithm.

3. The memory hub of claim 1, wherein the breakpoint circuit is configured to the breakpoint at an end of a packet.

4. The memory hub of claim 1, wherein the bypass circuit is coupled to the reception port through a bypass bus.

5. The memory hub of claim 1, further comprising a temporary memory coupled to the reception port and the breakpoint circuit, the breakpoint circuit further configured to selectively couple the reception port to the temporary memory, the temporary memory configured to store a digital signal received at the reception port when the reception port is not coupled to the transmission port.

6. The memory hub of claim 5 wherein the temporary memory comprises a FIFO memory.

7. A memory system comprising:

a memory controller; and

a memory hub coupled to the controller by an upstream link and a downstream link, the memory hub configured to control communications for the upstream link and the downstream link, the memory hub comprising;

an upstream transmission port coupled to the upstream link;

an upstream reception port configured to receive a digital signal;

a downstream transmission port configured to transmit a digital signal;

a downstream reception port coupled to the downstream link;

a local memory port;

at least one memory device coupled to the local memory port;

a downstream request routing circuit coupled to the downstream reception port, the local memory port and the downstream transmission port, the downstream request routing circuit being configured to determine whether a memory request transmitted from the memory controller to the downstream reception port through the downstream link is directed to the least one memory device coupled to the local memory port or to a downstream memory device, the downstream request routing circuit further being configured to couple the memory request to the local memory report responsive to a determination that the memory request is directed to a local memory device and to couple the digital signal received by the downstream reception port to the downstream transmission port responsive to a determination that the memory request is directed to a downstream memory device;

a bypass circuit coupled to the upstream transmission port, the upstream reception port, and the local memory port, the bypass circuit configured to selectively couple the upstream transmission port to the upstream reception port or the local memory port; and

a breakpoint circuit coupled to the bypass circuit configured to identify a breakpoint in a digital signal received from either the local memory port or the upstream reception port, and, responsive to the identification, to couple a control signal to the bypass circuit to initiate a switch between the upstream reception port and the local memory port.

8. The memory system of claim 7, further comprising a second memory hub coupled to the reception port by a second upstream link, the second memory hub configured to transmit a digital signal to the second upstream link.

9. The memory system of claim 7 wherein the breakpoint logic is configured to identify a breakpoint in a digital signal before the digital signal is applied to the memory hub.

10. The memory system of claim 7 wherein the breakpoint logic is configured to implement a switching algorithm.

11. The memory system of claim 7 wherein the digital signal that the reception port is configured to receive comprises a digital signal packet, and wherein the breakpoint logic is configured to identify an end of the packet as the breakpoint.

12. The memory system of claim 7 wherein the bypass circuit is coupled to the reception port through a bypass bus.

13. The memory system of claim 7 further comprising a temporary memory coupled to the reception port and the breakpoint circuit, the breakpoint circuit further configured to selectively couple the reception port to the temporary memory, the temporary memory configured to store data received at the reception port when the reception port is not coupled to the transmission port.

14. The memory system of claim 13 wherein the temporary memory comprises a FIFO memory.

15. A method for controlling communications on an upstream link and a downstream link between a memory module and a memory controller, the method comprising:

coupling the upstream link to an upstream bus of the memory module, the upstream bus being configured to pass data received at an upstream reception port of the memory hub;

coupling the downstream link to a downstream bus of the memory module, the bus being configured to pass memory requests received by the memory hub through the downstream link;

determining a local communication is available from a local memory in the memory module;

identifying a breakpoint in data on the upstream bus of the memory module;

coupling the upstream link to the local memory at the breakpoint to allow the upstream link to receive the local communication;

determining if the memory request on the downstream bus is directed to the local memory or to a downstream memory; and

routing a memory request on the downstream bus to the local memory responsive to a determination that the memory request is directed to the local memory and to the downstream transmission port of the memory hub responsive to a determination that the memory request is directed to a downstream memory.

16. The method of claim 15 wherein the memory module comprises a bypass circuit configured to selectively couple the local memory and the bus to the upstream link, the method further comprising coupling a signal to the bypass circuit to begin a switch prior to receiving the breakpoint on the bus.

17. The method of claim 15 wherein the act of identifying a breakpoint includes identifying a type of packet on the bypass bus.

18. The method of claim 15, further comprising storing further remote data received by the memory module in a temporary memory while the upstream link is coupled to the local memory.

19. The method of claim 18 wherein the temporary memory comprises a FIFO memory.

20. The method of claim 18 wherein the second temporary memory comprises a buffer memory.

21. The method of claim 18, further comprising identifying a second breakpoint after the local communication is coupled to the upstream link, and coupling the upstream link to the temporary memory to receive the further remote data responsive to detecting the second breakpoint.