Memory system comprising semiconductor memory having plural different operation modes

• US 7,949,818 B2
• Filed: 10/10/2006
• Issued: 05/24/2011
• Est. Priority Date: 10/21/2005
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suyama, Shoji
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Mackall; Larry T
• Application Number:
  US11/548,075
• Publication Number:
  US 20070127279A1
• Time in Patent Office: 1,687 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory system includes a nonvolatile semiconductor memory and a controller. The controller controls the nonvolatile semiconductor memory. The controller selects whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory;

a controller which controls the nonvolatile semiconductor memory, the controller selecting whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode; and

an I/O line which connects the controller to the nonvolatile semiconductor memory,

wherein the controller comprises;

a system clock generating section which generates a system clock which is used to determine control timing for the controller;

an input circuit to which read data from the nonvolatile semiconductor memory is input through the I/O line;

an output circuit which outputs write data to be written to the nonvolatile semiconductor memory through the I/O line; and

an I/O control circuit which controls the input circuit and the output circuit,

wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode so that read modes operate at different system clocks at different clock frequencies,

wherein the controller issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the nonvolatile semiconductor memory,

the nonvolatile semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, and

when the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode,

wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation in the controller, the fourth control signal being a chip enable signal in the controller, and

wherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, and

the transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal.

2. The system according to claim 1, wherein the controller determines whether to use the nonvolatile semiconductor memory in the first read mode or in the second read mode, in accordance with a read mode switching signal.

3. The system according to claim 2, wherein the controller comprises an external pin which receives the read mode switching signal.

4. The system according to claim 2, wherein the read mode switching signal is provided by a host instrument which uses the nonvolatile semiconductor memory as a recording medium.

5. The system according to claim 4, wherein,

the controller comprises a register, wherein

the register stores the read mode switching signal provided by the host instrument.

6. The system according to claim 2, wherein the read mode switching signal is provided by the nonvolatile semiconductor memory.

7. The system according to claim 6, wherein,

the controller comprises a register, wherein

the register stores the read mode switching signal provided by the host instrument.

8. The system according to claim 2, further comprising a switch circuit which fixes the read mode switching signal to “

0”

or “

1”

.

9. The system according to claim 2, wherein,

the controller includes a register which stores the read mode switching signal, and

a memory interface which is connectable to the nonvolatile semiconductor memory and which selects whether to use the nonvolatile semiconductor memory in the first read mode or in the second read mode in accordance with the read mode switching signal received from the register.

10. The system according to claim 9, wherein the memory interface receives the read mode switching signal from a host instrument through the register.

11. The system according to claim 9, wherein the memory interface receives the read mode switching signal from the nonvolatile semiconductor memory through the register.

12. The system according to claim 1, wherein the controller includes:

a read data loading circuit which loads the read data input to the input circuit, in response to an edge of the system clock, wherein

the read data loading circuit selects, depending on a determined read mode, whether to load the read data at a rising edge of the system clock or a falling edge of the system clock.

13. The system according to claim 1, wherein,

the controller outputs a second read mode entry command which enters the second read mode and a second read mode canceling command which cancels the entered second read mode, and

upon receiving the second read mode entry command, the nonvolatile semiconductor memory operates in the second read mode instead of the first read mode, and upon receiving the second read mode canceling command, the nonvolatile semiconductor memory operates in the first read mode instead of the second read mode.

14. The system according to claim 1, wherein the nonvolatile semiconductor memory operates in the first read mode after power-on and before receiving a second read mode entry command.

15. The system according to claim 1, wherein the first read mode is a serial read mode, and the second read mode is an extended data out mode.

16. The system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory.

17. The system according to claim 1, wherein a duty of the system clock in the first read mode is different from a duty of the system clock in the second read mode.

18. The system according to claim 1, wherein the I/O control circuit includes:

a first logical gate which performs a logical operation of the fourth control signal and a fifth control signal, the fifth control signal enabling a data write operation;

a second logical gate which performs a logical operation of the third control signal and an output of the first logical gate;

a first selection circuit which selects the third control signal in the first read mode, and selects an output of the second logical gate in the second read mode;

a flip-flop which receives an input signal and outputs the input signal as the second control signal; and

a second selection circuit which outputs a signal selected by the first selection circuit to the flip-flop as the input signal in the first read mode, and outputs the signal selected by the first selection circuit or the second control signal to the flip-flop as the input signal in accordance with third, fourth, and fifth control signals in the second read mode.

19. A recording medium comprising:

a nonvolatile semiconductor memory;

a controller which controls the nonvolatile semiconductor memory and which selects whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode; and

an I/O line which connects the controller to the nonvolatile semiconductor memory,

wherein the controller includes;

a system clock generating section which generates a system clock which is used to determine control timing for the controller;

an input circuit to which read data from the nonvolatile semiconductor memory is input through the I/O line;

an output circuit which outputs write data to be written to the nonvolatile semiconductor memory through the I/O line; and

an I/O control circuit which controls the input circuit and the output circuit,

wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode so that read modes operates at different system clock at different clock frequencies,

wherein the controller issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the nonvolatile semiconductor memory,

the nonvolatile semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, and

when the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode,

wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation in the controller, the fourth control signal being a chip enable signal in the controller, and

wherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, and

the transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal.

20. A memory controller comprising:

a host interface which is connectable to a host instrument;

a memory interface which is connectable to a semiconductor memory, the memory interface selecting whether to use the semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode;

a system clock generating section which generates a system clock which is used to determine control timing for the controller;

an input circuit to which read data from the semiconductor memory is input through an I/O line, the I/O line connecting the memory interface to the semiconductor memory;

an output circuit which outputs write data to be written to the semiconductor memory through the I/O line; and

an I/O control circuit which controls the input circuit and the output circuit,

wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode,

wherein the memory interface issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the semiconductor memory,

the semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, and

when the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode,

wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation, the fourth control signal being a chip enable signal in the memory controller, and

wherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, and

the transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal.

21. The controller according to claim 20, further comprising:

a read data loading circuit which loads the read data input to the input circuit, in response to an edge of the system clock, wherein

the read data loading circuit selects, depending on a determined read mode, whether to load the read data at a rising edge of the system clock or a falling edge of the system clock.