Memory system comprising semiconductor memory having plural different operation modes
First Claim
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1. A memory system comprising:
- a nonvolatile semiconductor memory;
a controller which controls the nonvolatile semiconductor memory, the controller selecting whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode; and
an I/O line which connects the controller to the nonvolatile semiconductor memory,wherein the controller comprises;
a system clock generating section which generates a system clock which is used to determine control timing for the controller;
an input circuit to which read data from the nonvolatile semiconductor memory is input through the I/O line;
an output circuit which outputs write data to be written to the nonvolatile semiconductor memory through the I/O line; and
an I/O control circuit which controls the input circuit and the output circuit,wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode so that read modes operate at different system clocks at different clock frequencies,wherein the controller issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the nonvolatile semiconductor memory,the nonvolatile semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, andwhen the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode,wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation in the controller, the fourth control signal being a chip enable signal in the controller, andwherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, andthe transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal.
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Abstract
A memory system includes a nonvolatile semiconductor memory and a controller. The controller controls the nonvolatile semiconductor memory. The controller selects whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode.
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Citations
21 Claims
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1. A memory system comprising:
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a nonvolatile semiconductor memory; a controller which controls the nonvolatile semiconductor memory, the controller selecting whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode; and an I/O line which connects the controller to the nonvolatile semiconductor memory, wherein the controller comprises; a system clock generating section which generates a system clock which is used to determine control timing for the controller; an input circuit to which read data from the nonvolatile semiconductor memory is input through the I/O line; an output circuit which outputs write data to be written to the nonvolatile semiconductor memory through the I/O line; and an I/O control circuit which controls the input circuit and the output circuit, wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode so that read modes operate at different system clocks at different clock frequencies, wherein the controller issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the nonvolatile semiconductor memory, the nonvolatile semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, and when the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode, wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation in the controller, the fourth control signal being a chip enable signal in the controller, and wherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, and the transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A recording medium comprising:
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a nonvolatile semiconductor memory; a controller which controls the nonvolatile semiconductor memory and which selects whether to use the nonvolatile semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode; and an I/O line which connects the controller to the nonvolatile semiconductor memory, wherein the controller includes; a system clock generating section which generates a system clock which is used to determine control timing for the controller; an input circuit to which read data from the nonvolatile semiconductor memory is input through the I/O line; an output circuit which outputs write data to be written to the nonvolatile semiconductor memory through the I/O line; and an I/O control circuit which controls the input circuit and the output circuit, wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode so that read modes operates at different system clock at different clock frequencies, wherein the controller issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the nonvolatile semiconductor memory, the nonvolatile semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, and when the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode, wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation in the controller, the fourth control signal being a chip enable signal in the controller, and wherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, and the transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal.
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20. A memory controller comprising:
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a host interface which is connectable to a host instrument; a memory interface which is connectable to a semiconductor memory, the memory interface selecting whether to use the semiconductor memory in a first read mode or in a second read mode having shorter access intervals than the first read mode; a system clock generating section which generates a system clock which is used to determine control timing for the controller; an input circuit to which read data from the semiconductor memory is input through an I/O line, the I/O line connecting the memory interface to the semiconductor memory; an output circuit which outputs write data to be written to the semiconductor memory through the I/O line; and an I/O control circuit which controls the input circuit and the output circuit, wherein the system clock generating section changes a frequency of the system clock in accordance with a determined read mode, wherein the memory interface issues a first control signal in a data read operation, the first control signal performing as a clock for data read from the semiconductor memory, the semiconductor memory outputs read data to the input circuit, via the I/O line, in synchronization with assertion of the first control signal, and when the first control signal is negated, the I/O line is set to a high impedance state in the first read mode, and keeps the read data without being set to the high impedance state in the second read mode, wherein the I/O control circuit generates a second control signal to enable the input circuit and to disable the output circuit based on a third control signal and a fourth control signal, the third control signal enabling the data read operation, the fourth control signal being a chip enable signal in the memory controller, and wherein the I/O control circuit negates the second control signal to disable the input circuit in synchronization with a transition of a logical level of the third control signal in the first read mode, and in synchronization with a transition of a logical level of the fourth control signal in the second read mode, and the transition of the logical level of the fourth control signal occurs after the transition of the logical level of the third control signal. - View Dependent Claims (21)
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Specification