Balanced adaptive body bias control

• US 7,949,864 B1
• Filed: 09/28/2005
• Issued: 05/24/2011
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Svilan, Vjekoslav, Burr, James B.
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Rahman; Fahmida
• Application Number:
  US11/238,446
• Time in Patent Office: 2,064 Days
• Field of Search: 713/1, 713/2, 713/100, 713/300, 713/310, 713320-324, 713/330, 713/340, 326/36
• US Class Current: 713/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

Claims

1. A method comprising:

determining a desirable dynamic condition for a circuit of an integrated circuit, wherein the circuit receives a first and a second body biasing voltages;

accessing a first dynamic indicator of the circuit corresponding to the desirable dynamic condition;

accessing second and third dynamic indicators of the circuit;

adjusting the first body biasing voltage to change the first dynamic indicator in the direction of the desirable dynamic condition; and

adjusting the second body biasing voltage based on a relationship between the second dynamic indicator and the third dynamic indicator.

2. The method of claim 1 wherein the relationship comprises a difference between the second dynamic indicator and a scaled value of the third dynamic indicator and further wherein the adjusting acts to minimize the difference.

3. The method of claim 1 wherein the desirable dynamic condition corresponds to a desirable operating frequency for the integrated circuit.

4. The method of claim 1 wherein the first dynamic indicator corresponds to a gate delay of circuitry of the integrated circuit.

5. The method of claim 1 wherein the first dynamic indicator corresponds to on current of active devices of the integrated circuit.

6. The method of claim 1 wherein the second dynamic indicator corresponds to leakage current of a first polarity of active devices of the integrated circuit.

7. The method of claim 6 wherein the third dynamic indicator corresponds to leakage current of active devices of a second polarity opposite to the first polarity.

8. The method of claim 1 wherein the first dynamic indicator corresponds to a critical path replica of the integrated circuit.

9. The method of claim 1 further comprising delaying an interval for changes in body biasing voltages to have an effect.

10. The method of claim 1 further comprising repeating the determining, the accessing the first dynamic indicator, the accessing the second and third dynamic indicators, the adjusting the first body biasing voltage and the adjusting the second body biasing voltage.

11. The method of claim 1 wherein the accessing the first dynamic indicator comprises accessing a register value corresponding to the first dynamic indicator.

12. The method of claim 1 wherein the adjusting the first body biasing voltage by an increment comprises adjusting the first body biasing voltage by a minimum increment of adjustment available from a body biasing voltage supply.

13. The method of claim 1 wherein the integrated circuit is a microprocessor.

14. The method of claim 1 wherein the first body biasing voltage has a greater effect on the desirable dynamic condition than the second body biasing voltage.

15. A computer system comprising:

a microprocessor integrated circuit;

first and second body biasing voltage supplies coupled to the microprocessor integrated circuit for furnishing selectable voltages to first and second body biasing wells of the microprocessor integrated circuit;

a memory space coupled to the microprocessor integrated circuit and comprising instructions to implement a method of balanced adaptive body bias control comprising;

determining a desirable dynamic condition for circuitry of the microprocessor integrated circuit;

accessing a first dynamic indicator corresponding to the desirable dynamic condition;

accessing second and third dynamic indicators of the integrated circuit;

adjusting the first body biasing voltage supply to change the first dynamic indicator in the direction of the desirable dynamic condition; and

adjusting the second body biasing voltage supply based on a relationship between the second dynamic indicator and the third dynamic indicator.

16. The system of claim 15 wherein the desirable dynamic condition corresponds to a desirable operating frequency for the microprocessor integrated circuit.

17. The system of claim 16 wherein the first dynamic indicator corresponds to a gate delay of circuitry of the microprocessor integrated circuit.

18. The system of claim 15 wherein the accessing the first dynamic indicator comprises accessing a register value in an address space of the microprocessor integrated circuit corresponding to the first dynamic indicator.

19. The system of claim 15 wherein the adjusting the first body biasing voltage supply by an increment comprises adjusting the first body biasing voltage supply by a minimum increment of adjustment available from the first body biasing voltage supply.

20. The system of claim 15 wherein the first body biasing voltage has a greater effect on the desirable dynamic condition than the second body biasing voltage.

21. An article of manufacture including a computer usable media comprising instructions stored thereon that, responsive to execution on a computing device, cause the computing device to perform operations comprising:

determining a desirable dynamic condition for circuitry of an integrated circuit;

accessing a first dynamic indicator corresponding to the desirable dynamic condition;

accessing second and third dynamic indicators of the integrated circuit;

adjusting a first body biasing voltage so as to change the first dynamic indicator in the direction of the desirable dynamic condition; and

adjusting a second body biasing voltage based on a relationship between the second dynamic indicator and the third dynamic indicator.

22. The article of manufacture of claim 21 wherein the desirable dynamic condition corresponds to a desirable operating frequency for the integrated circuit.

23. The article of manufacture of claim 21 wherein the first dynamic indicator corresponds to a gate delay of circuitry of the integrated circuit.

24. The article of manufacture of claim 21 wherein the accessing the first dynamic indicator comprises accessing a register value corresponding to the first dynamic indicator.

25. The article of manufacture of claim 21 wherein the adjusting the first body biasing voltage comprises adjusting the first body biasing voltage by a minimum increment of adjustment available from a body biasing voltage supply.

26. A method comprising:

determining a desirable dynamic condition for a circuit of an integrated circuit, wherein the circuit receives a first well and a second well body biasing voltages;

accessing a first dynamic indicator of the circuit corresponding to the desirable dynamic condition;

accessing second and third dynamic indicators of the circuit;

adjusting the first well body biasing voltage to change the first dynamic indicator in the direction of the desirable dynamic condition; and

adjusting the second well body biasing voltage based on a relationship between the second dynamic indicator and the third dynamic indicator.

27. The method of claim 26 wherein the relationship comprises a difference between the second dynamic indicator and a non-unity scaled value of the third dynamic indicator and further wherein the adjusting acts to minimize the difference.

28. The method of claim 26 wherein the desirable dynamic condition corresponds to a desirable operating frequency for the integrated circuit.

29. The method of claim 26 wherein the first dynamic indicator corresponds to a gate delay of circuitry of the integrated circuit.

30. The method of claim 26 wherein the first dynamic indicator corresponds to on current of active devices of the integrated circuit.

31. The method of claim 26 wherein the second dynamic indicator corresponds to leakage current of a first polarity of active devices of the integrated circuit.

32. The method of claim 31 wherein the third dynamic indicator corresponds to leakage current of active devices of a second polarity opposite to the first polarity.

33. An integrated circuit comprising:

means for determining a desirable dynamic condition for a circuit of the integrated circuit, wherein the circuit receives a first well and a second well body biasing voltages;

means for accessing a first dynamic indicator of the circuit corresponding to the desirable dynamic condition;

means for accessing second and third dynamic indicators of the circuit;

means for adjusting the first body biasing voltage to change the first dynamic indicator in the direction of the desirable dynamic condition; and

means for adjusting the second body biasing voltage based on a relationship between the second dynamic indicator and the third dynamic indicator.

34. The integrated circuit of claim 33 wherein the first dynamic indicator corresponds to a critical path replica of the integrated circuit.

35. The integrated circuit of claim 33 further comprising delaying an interval for changes in body biasing voltages to have an effect.

36. The integrated circuit of claim 33 further comprising means for repeating the determining, the accessing the first dynamic indicator, the accessing the second and the third dynamic indicators, the adjusting the first body biasing voltage and the adjusting the second body biasing voltage.

37. The integrated circuit of claim 33 wherein the means for accessing the first dynamic indicator comprises accessing a register value corresponding to the first dynamic indicator.

38. The integrated circuit of claim 33 wherein the means for adjusting the first body biasing voltage by an increment comprises adjusting the first well body biasing voltage by a minimum increment of adjustment available from a body biasing voltage supply.

39. The integrated circuit of claim 33 wherein the integrated circuit is a microprocessor.

40. The integrated circuit of claim 33 wherein the first well body biasing voltage has a greater effect on the desirable dynamic condition than the second well body biasing voltage.