Layout circuit having a combined tie cell

• US 7,949,988 B2
• Filed: 04/01/2008
• Issued: 05/24/2011
• Est. Priority Date: 04/01/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lin, Chih-Ching, Tsai, Tung-Kai
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US12/060,298
• Publication Number:
  US 20090249273A1
• Time in Patent Office: 1,148 Days
• Field of Search: 716/55, 716/104, 716118-120, 716/122, 716132-133, 716/139, 326/27, 326/104, 326/122
• US Class Current: 716/139
• CPC Class Codes: G06F 2117/06 Spare resources, e.g. for permanent fault suppression
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

Claims

1. A circuit layout method, comprising:

placing and routing standard cells on a layout area;

adding a spare cell on the layout area, wherein the spare cell is provided for replacing one of the standard cells while adding or changing function; and

adding a combined tie cell on the layout area for tying a voltage provided to the replaced standard cell, wherein the combined tie cell is independent of the standard cells.

2. The circuit layout method as claimed in claim 1, wherein the combined tie cell comprises a tie-high circuit arranged to make connection between a first supplied voltage and the replaced standard cell and a tie-low circuit arranged to make connection between a second supplied voltage and the replaced standard cell.

3. The circuit layout method as claimed in claim 2, wherein the tie-high circuit comprises:

a first PMOS transistor comprising a gate terminal, a source terminal coupled to the first supplied voltage, and a drain terminal for providing a first tied voltage; and

a first NMOS transistor comprising a drain terminal and a gate terminal coupled to the gate terminal of the first PMOS transistor, and a source terminal coupled to the second supplied voltage; and

the tie-low circuit comprises;

a second PMOS transistor comprising a source terminal coupled to the first supplied voltage, and a gate terminal and a drain terminal; and

a second NMOS transistor comprising a drain terminal for providing a second tied voltage, a gate terminal coupled to the gate terminal and the drain terminal of the second PMOS transistor, and a source terminal coupled to the second supplied voltage.

4. The circuit layout method as claimed in claim 1, wherein the combined tie cell comprises a tie-high circuit arranged to make connection between a first supplied voltage and the replaced standard cell, a tie-low circuit arranged to make connection between a second supplied voltage and the replaced standard cell and a capacitance circuit for voltage stability.

5. The circuit layout method as claimed in claim 1, wherein the combined tie cell is disposed near the replaced standard cell.

6. The circuit layout method as claimed in claim 1, wherein the combined tie cell is disposed near the snare cell.

7. The circuit layout method as claimed in claim 1, wherein a voltage provided to the spare cell is initially tied by the combined tie cell before adding or changing function.

8. The circuit layout method as claimed in claim 1, wherein the spare cell is an OR gate, AND gate, MUX, flip flop or inverter prepared for an engineering change order.

9. A layout circuit, comprising:

standard cells disposed on a layout area;

a spare cell disposed on the layout area, wherein the spare cell is provided for replacing one of the standard cells; and

a combined tie cell disposed on the layout area for tying a voltage provided to the replaced standard cell, wherein the combined tie cell is independent of the standard cells.

10. The layout circuit as claimed in claim 9, wherein the combined tie cell comprises a tie-high circuit arranged to make connection between a first supplied voltage and the replaced standard cell and a tie-low circuit arranged to make connection between a second supplied voltage and the replaced standard cell.

11. The layout circuit as claimed in claim 10, wherein the tie-high circuit comprises:

a first PMOS transistor comprising a gate terminal, a source terminal coupled to the first supplied voltage, and a drain terminal for providing a first tied voltage; and

a first NMOS transistor comprising a drain terminal and a gate terminal coupled to the gate terminal of the first PMOS transistor, and a source terminal coupled to the second supplied voltage; and

the tie-low circuit comprises;

a second PMOS transistor comprising a source terminal coupled to the first supplied voltage, and a gate terminal and a drain terminal; and

a second NMOS transistor comprising a drain terminal for providing a second tied voltage, a gate terminal coupled to the gate terminal and the drain terminal of the second PMOS transistor, and a source terminal coupled to the second supplied voltage.

12. The layout circuit as claimed in claim 9, wherein the combined tie cell comprises a tie-high circuit arranged to make connection between a first supplied voltage and the replaced standard cell, a tie-low circuit arranged to make connection between a second supplied voltage and the replaced standard cell and a capacitance circuit for voltage stability.

13. The layout circuit as claimed in claim 9, wherein the combined tie cell is disposed near the replaced standard cell.

14. The layout circuit as claimed in claim 9, wherein the combined tie cell is disposed near the spare cell.

15. The layout circuit as claimed in claim 9, wherein a voltage provided to the spare cell is initially tied by the combined tie cell before the spare cell replaces one of the standard cells.

16. The layout circuit as claimed in claim 9, wherein the spare cell is an OR gate, AND gate, MUX, flip flop or inverter prepared for an engineering change order.