Parallel electronic design automation: shared simultaneous editing

• US 7,949,990 B2
• Filed: 04/06/2010
• Issued: 05/24/2011
• Est. Priority Date: 12/10/2001
• Status: Expired due to Fees

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Natarajan, Venkat, Potts, Henry, Smith, Edwin Franklin, Petunin, Vladimir, Pfeil, Charles
• Primary Examiner(s): Levin; Naum
• Application Number:
  US12/754,850
• Publication Number:
  US 20100199240A1
• Time in Patent Office: 413 Days
• Field of Search: 716/119, 716/137, 716/139, 715/733, 715/751
• US Class Current: 716/139
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Claims

1. A method comprising

maintaining a master printed circuit board design on a server computer;

displaying at least a portion of the master printed circuit board design to a user on a client computer;

receiving an edit command to edit the master printed circuit board design at the client computer;

executing the edit command on the client computer to produce an edit for the master printed circuit board design;

providing the edit to the server computer to implement in the master printed circuit board design;

determining if the edit will create an error in the master printed circuit board design; and

if it is determined that the edit will not create an error in the master printed circuit board design, then making the edit to the master circuit design.

2. A method comprising

maintaining a master circuit design on a server computer;

displaying at least a portion of the master circuit design to a user on a client computer;

receiving an edit command to edit the master circuit design at the client computer;

determining at the client computer if the edit will create an error in the master circuit design; and

determining at the server computer if the edit will create an error in the master circuit design.

3. The method recited in claim 2, further comprising:

if it is determined at the client computer that the edit will not create an error in the master circuit design; and

if it is determined at the server computer that the edit will not create an error in the master circuit design;

then making the edit to the master circuit design.