Method for producing a thin semiconductor chip comprising an integrated circuit

• US 7,951,691 B2
• Filed: 09/11/2008
• Issued: 05/31/2011
• Est. Priority Date: 03/14/2006
• Status: Active Grant

• Current Assignee: Institut fuer Mikroelektronik Stuttgart
• Original Assignee: Institut fuer Mikroelektronik Stuttgart
• Inventors: Zimmermann, Martin, Appel, Wolfgang, Burghartz, Joachim N.
• Primary Examiner(s): Smith; Matthew S
• Assistant Examiner(s): Jefferson; Quovaunda
• Application Number:
  US12/208,514
• Publication Number:
  US 20090096089A1
• Time in Patent Office: 992 Days
• Field of Search: 438/455, 438/458, 438/FOR.106, 438/FOR.108, 438/FOR.231, 438/460, 438/462, 438/705, 438/FOR.408, 257/E21.287, 257/E21.568, 257/E21.57
• US Class Current: 438/462
• CPC Class Codes: H01L 21/02002 Preparing wafers
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off

Abstract

In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer.

Claims

1. A method for producing a thin semiconductor chip comprising an integrated circuit, the method comprising the steps of:

providing a semiconductor wafer having a first and a second surface, the semiconductor wafer being composed of p-doped silicon in the region of the first surface,

defining at least one wafer section in the region of the first surface,

converting the p-doped silicon in the region of the defined wafer section into porous silicon having a plurality of pores by means of an anodic etching process, the porous silicon comprising an upper layer at the first surface and a lower layer below the upper layer,

producing a wafer cavity below the at least one defined wafer section by thermally treating the porous silicon such that the pores of the upper layer are substantially closed by material from the lower layer,

producing a circuit structure in the at least one defined wafer section, and

releasing the defined wafer section from the semiconductor wafer,

wherein the wafer section is freed in a first process sequence by etching trenches into the depth of the wafer such that it is held only via web connections arranged at the lateral periphery of the wafer section on the remaining semiconductor wafer,

wherein the web connections are severed in a second process sequence, and

wherein a plurality of local n-doped regions are produced in the p-doped silicon before the p-doped silicon is converted into porous silicon by means of the anodic etching process.

2. The method of claim 1, wherein the wafer cavity below the defined wafer section is produced as a closed wafer cavity.

3. The method of claim 1, wherein the cavity has a lateral area extent that substantially matches the defined wafer section.

4. The method of claim 1, wherein a first group of strip-like n-doped regions are produced, which strip-like regions form an n-doped lattice structure with enclosed p-doped facets at the first surface.

5. The method of claim 1, wherein a second group of spot-like n-doped regions are produced, wherein at least one spot-like n-doped region is arranged in the region of the defined wafer section.

6. The method of claim 5, wherein a ring-shaped n-doped region is produced, and wherein the spot-like n-doped regions are distributed substantially uniformly within the ring-shaped n-doped region.

7. The method of claim 6, wherein the ring-shaped n-doped region is arranged substantially concentrically with respect to the wafer.

8. The method of claim 1, wherein an epitaxial layer is applied to the first surface after thermally treating the porous silicon, and wherein the circuit structure is produced at least predominantly in the epitaxial layer.

9. The method of claim 1, wherein the defined wafer section is freed after the circuit structure has been produced.

10. The method of claim 1, wherein the wafer has a crystal lattice having a [100] direction and a [110] direction, wherein the defined wafer section is arranged parallel to the [100] direction or parallel to the [110] direction, and wherein the web local connections are arranged at corners or at lateral edges of the wafer section.

11. The method of claim 1, wherein the p-doped silicon is converted into the upper layer composed of porous silicon having a plurality of finer pores and into the lower layer having a plurality of larger pores by means of the anodic etching process.

12. The method of claim 1, wherein the semiconductor wafer at the first surface has a top layer at the first surface and a bottom layer remote from the first surface, wherein the top layer is composed of a more heavily p-doped silicon than the bottom layer.

13. The method of claim 1, wherein the semiconductor wafer is ground after the defined wafer section has been released in order to re-use the semiconductor wafer for the production of further integrated circuit chips.

14. The method of claim 1, wherein the second process sequence comprises breaking out the wafer section by means of shear forces.

15. A method for producing a thin semiconductor chip comprising an integrated circuit, the method comprising the steps of:

providing a semiconductor wafer having a first and a second surface, the semi-conductor wafer being composed of p-doped silicon in the region of the first surface,

defining at least one wafer section in the region of the first surface,

converting the p-doped silicon in the region of the defined wafer section into porous silicon having a plurality of pores by means of an anodic etching process, the porous silicon comprising an upper layer at the first surface and a lower layer below the upper layer,

producing a wafer cavity below the at least one defined wafer section by thermally treating the porous silicon such that the pores of the upper layer are substantially closed by material from the lower layer,

producing a circuit structure in the at least one defined wafer section, and

releasing the defined wafer section from the semiconductor wafer,

wherein the wafer section is freed in a first process sequence such that it is held only via web connections on the remaining semiconductor wafer, and

wherein the web connections are severed in a second process sequence,

wherein a plurality of local n-doped regions are produced in the p-doped silicon before the p-doped silicon is converted into porous silicon by means of the anodic etching process.

16. The method of claim 15, wherein a first group of strip-like n-doped regions are produced, which strip-like regions form an n-doped lattice structure with enclosed p-doped facets at the first surface.

17. The method of claim 15, wherein a second group of spot-like n-doped regions are produced, wherein at least one spot-like n-doped region is arranged in the region of the defined wafer section.

18. The method of claim 17, wherein a ring-shaped n-doped region is produced, and wherein the spot-like n-doped regions are distributed substantially uniformly within the ring-shaped n-doped region.

19. The method of claim 18, wherein the ring-shaped n-doped region is arranged substantially concentrically with respect to the wafer.