Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout

• US 7,952,139 B2
• Filed: 06/30/2008
• Issued: 05/31/2011
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Bhalla, Anup, Ho, Moses
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US12/217,092
• Publication Number:
  US 20080265312A1
• Time in Patent Office: 1,065 Days
• Field of Search: 257/330, 257/334, 257/E27.04, 257/E29.013, 257/475, 257/476, 257/484
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Claims

1. A semiconductor power device comprising an active cell area having a plurality of power transistor cells supported on a semiconductor substrate, wherein:

said power transistor cells are integrated and functioning together with a plurality of Schottky diodes disposed in areas between said power transistor cells on said semiconductor substrate wherein said Schottky diodes disposed between said active transistor cells comprise separated body dopant regions near a top surface of said semiconductor substrate cover under a Schottky junction barrier metal and wherein said separated body dopant regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer and having an opposite conductivity type from said separated body dopant regions; and

each of said power transistor cells comprising a trenched gate surrounded by a body region encompassing a source region therein and one of said separated body dopant regions is disposed in an outer upper edge in one of said body regions as a junction barrier Schottky (JBS) body region of one of said power transistor cells wherein said JBS body region disposed next to said Schottky diodes has no source region encompassed therein.

2. The semiconductor power device of claim 1 wherein:

each of said separated body dopant regions is further surrounded by a lightly body dopant region with a body dopant concentration lower than said separated body dopant regions.

3. The semiconductor power device of claim 1 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

4. The semiconductor power device of claim 1 wherein:

said power transistor cells are configured to surround an area as a junction barrier Schottky (JBS) pocket region with said separated body dopant regions disposed therein surrounded by said power transistor cells and covered by said Schottky junction barrier metal on top of said semiconductor substrate.

5. The semiconductor power device of claim 1 wherein each of said power transistor cells further comprising:

said power transistor cells comprising MOSFET transistor cells and configured to surround an area as a junction barrier Schottky (JBS) pocket region with said separated body dopant regions disposed therein surrounded by said MOSFET transistor cells and covered by said Schottky junction barrier metal on top of said semiconductor substrate.

6. The semiconductor power device of claim 1 wherein

said upper source dopant layer comprises a boron dopant layer.

7. The semiconductor power device of claim 1 wherein:

said upper source dopant layer and said lower source dopant layer further comprise an epitaxial layer having the smaller and greater source dopant concentration respectively disposed in said semiconductor substrate.

8. A semiconductor power device comprising an active cell area having a plurality of power transistor cells supported on a semiconductor substrate, wherein:

said power transistor cells are configured to surround a semiconductor area as a junction barrier Schottky (JBS) pocket region to form a plurality of planar Schottky diodes therein each comprising a separated body dopant region covered under a Schottky junction barrier metal on top of said semiconductor substrate; and

each of said power transistor cells comprising a trenched gate surrounded by a body region encompassing a source region therein and one of said separated body dopant regions is disposed in an outer upper edge in one of said body regions as a junction barrier Schottky (JBS) body region of one of said power transistor cells wherein said JBS body region disposed next to said Schottky diodes has no source region encompassed therein.

9. The semiconductor power device of claim 8 wherein:

said separated body dopant regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer and having an opposite conductivity type from said separated body dopant regions.

10. The semiconductor power device of claim 9 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

11. The semiconductor power device of claim 9 wherein

said upper source dopant layer comprises a boron dopant layer.

12. The semiconductor power device of claim 9 wherein:

said upper source dopant layer and said lower source dopant layer further comprise an epitaxial layer having the smaller and greater source dopant concentration respectively disposed in said semiconductor substrate.

13. The semiconductor power device of claim 8 wherein:

each of said power transistor cells comprising a trenched gate surrounded by a body region encompassing a source region therein and said power transistor cells disposed adjacent to said JBS pocket region comprising said body region having no source region encompassed therein.

14. The semiconductor power device of claim 8 wherein:

each of said separated body dopant regions is further surrounded by a lightly body dopant region with a body dopant concentration lower than said separated body dopant regions.

15. The semiconductor power device of claim 8 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

16. The semiconductor power device of claim 8 wherein:

said semiconductor power device comprising a plurality of metal oxide field effect transistor (MOSFET) cells.

17. A semiconductor power device comprising:

a semiconductor substrate supports an epitaxial layer having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer;

an active cell area having a plurality of power transistor cells configured to surround a semiconductor area as a junction barrier Schottky (JBS) pocket region to form a plurality of a planar Schottky diodes therein each comprising a separated body dopant region formed near the top surface of said epitaxial layer surrounded by said epitaxial layer having the lighter dopant concentration and covered under a Schottky junction barrier metal on top of said semiconductor substrate; and

each of said power transistor cells comprising a trenched gate surrounded by a body region encompassing a source region therein and one of said separated body dopant regions is disposed in an outer upper edge in one of said body regions as a junction barrier Schottky (JBS) body region of one of said power transistor cells wherein said JBS body region disposed next to said Schottky diodes has no source region encompassed therein.

18. The semiconductor power device of claim 17 further comprising:

a Shannon implant region disposed in a gap between said separated body dopant regions of two adjacent power transistor cells.