Isolation circuit
First Claim
1. An isolation circuit, comprising:
- a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal;
a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal;
a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential;
a first fuse device coupling the second source/drain terminal to a node;
a second fuse device coupling the node to the first pad;
a third pad operable to receive a signal to be applied to at least one die; and
a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node;
wherein the first transistor, the second transistor, the first pad, the second pad, the first fuse device, and the second fuse device are in a scribe line formed on a wafer including the at least one die.
7 Assignments
0 Petitions
Accused Products
Abstract
An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.
-
Citations
15 Claims
-
1. An isolation circuit, comprising:
-
a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal; a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal; a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential; a first fuse device coupling the second source/drain terminal to a node; a second fuse device coupling the node to the first pad; a third pad operable to receive a signal to be applied to at least one die; and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node; wherein the first transistor, the second transistor, the first pad, the second pad, the first fuse device, and the second fuse device are in a scribe line formed on a wafer including the at least one die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An isolation circuit, comprising:
-
a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal; a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal; a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential; a first fuse device coupling the second source/drain terminal to a node; a second fuse device coupling the node to the first pad; a third pad operable to receive a first signal; and a second transistor operable to selectively couple the third pad to at least one die in response to a control signal provided by the node; wherein the first transistor, the first pad, the second pad, the first fuse device, and the second fuse device are in a scribe line of a wafer, and the second transistor is in a die on the wafer. - View Dependent Claims (13, 14, 15)
-
Specification