Semiconductor device with hollow structure

• US 7,952,185 B2
• Filed: 12/22/2006
• Issued: 05/31/2011
• Est. Priority Date: 12/08/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Beer, Gottfried, Theuss, Horst
• Primary Examiner(s): Vu; David
• Assistant Examiner(s): CHI, SUBERR L
• Application Number:
  US11/645,150
• Publication Number:
  US 20080136009A1
• Time in Patent Office: 1,621 Days
• Field of Search: 257/678, 257/698, 257/684, 257/690, 257/709, 257/734, 257/738, 257/787, 257/788, 257/E21.502, 438/106
• US Class Current: 257/690
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0154 Moulding a cap over the MEMS device
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.

Claims

1. A device, comprising:

a chip, which is held in a casting compound and on which a hollow structure is arranged, the casting compound and the hollow structure each forming part of a surface of the device which extends substantially in parallel to a principal plane of the chip;

a dielectric layer,

a first electrically conductive layer overlying at least a part of a surface formed by the casting compound and a part of a surface being formed by the hollow structure, wherein the first electrically conductive layer is arranged between the chip and the dielectric layer, and

wherein the hollow structure is arranged between the chip and a portion of the first electrically conductive layer in relation to a direction normal to the principal plane.

2. The device of claim 1 wherein the hollow structure is arranged over an active area of the chip.

3. The device of claim 1, wherein an upper side of the hollow structure is not covered by casting compound.

4. The device of claim 3, wherein a chip surface opposite from an active surface of the chip, all the side areas of the chip, and side areas of the hollow structure are surrounded by casting compound.

5. The device of claim 1, further comprising a wiring structure comprising the first electrically conductive layer, at least one dielectric layer, and a second electrically conductive layer.

6. The device of claim 5, wherein the wiring structure extends in a direction parallel to the principal plane outwards beyond the contour of the chip.

7. The device according to claim 5, wherein the hollow structure is arranged between an active area of the chip and the wiring structure in a direction normal to the principal plane.

8. The device of claim 1, wherein a plurality of hollow structures are arranged over an active area of the chip.

9. The device of claim 1, wherein the hollow structure is a hollow structure comprising a polymer material.

10. The device of claim 9, wherein the hollow structure comprises an upper side facing away from the chip,

wherein the upper side is not covered by casting compound and forms part of the surface of the device;

and

wherein the first electrically conductive layer extends over at least a part of the upper side of the hollow structure.

11. The device of claim 9, wherein the polymer material is a photoresist.

12. The device of claim 1, wherein the hollow structure further comprises a first surface facing towards the chip and a second surface opposite to the first surface facing away from the chip, wherein the second surface forms part of the surface of the device.

13. A device, comprising:

a chip, which is held in a casting compound and on which a hollow structure is arranged, the hollow structure having a lid and a sidewall, the sidewall enclosing a portion of the chip, extending between a surface of the chip and the lid, and the lid at least partially covering the portion of the chip; and

a first electrically conductive layer, which has been applied at least in certain regions to the casting compound;

wherein the lid of the hollow structure comprises a through-hole for connecting the hollow structure to its surroundings, the through-hole being hollow, and

wherein the first electrically conductive layer and the through-hole are arranged at a same side of the chip.