System and method for coherent frequency switching in DDS architectures
First Claim
1. An integrated circuit device comprising:
- a primary signal synthesizer including a primary frequency accumulator in series with a primary phase accumulator, the primary frequency accumulator being configured to generate a primary digital modulation signal based on a predetermined modulation format and a primary frequency, the primary phase accumulator being configured to increment in response to a digital clock signal to thereby generate a free-running primary digital signal in accordance with the primary modulation signal;
at least one secondary signal synthesizer disposed in parallel with the primary signal synthesizer, the at least one secondary signal synthesizer including at least one secondary frequency accumulator in series with a corresponding one of at least one secondary phase accumulator, the at least one secondary frequency accumulator being configured to generate at least one secondary digital modulation signal based on at least one secondary frequency, the at least one secondary phase accumulator being configured to increment in response to the digital clock signal to thereby generate a free-running at least one secondary digital signal in accordance with the at least one secondary digital modulation signal; and
a switch element including a first switch input coupled to the primary signal synthesizer and at least one second switch input coupled to the at least one secondary signal synthesizer, the switch element being configured to select a switch output that provides either the primary digital signal or the at least one secondary digital signal based on a switch control input, a latter switch element output of the primary digital signal provided after the switch element output the at least one secondary digital signal being phase coherent with a former switch output of the primary digital signal provided before the switch element output the at least one secondary digital signal.
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Abstract
The present invention is directed to an integrated circuit device that includes a primary signal synthesizer configured to generate a free-running first digital frequency signal and at least one secondary signal synthesizer disposed in parallel with the primary signal synthesizer and configured to generate a free-running at least one second digital frequency signal. A switch element includes a first switch input coupled to the primary signal synthesizer and at least one second switch input coupled to the at least one secondary signal synthesizer. The switch element is configured to select a switch output that provides either the free-running first digital frequency signal or the free-running at least one second digital frequency signal based on a switch control input.
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Citations
36 Claims
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1. An integrated circuit device comprising:
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a primary signal synthesizer including a primary frequency accumulator in series with a primary phase accumulator, the primary frequency accumulator being configured to generate a primary digital modulation signal based on a predetermined modulation format and a primary frequency, the primary phase accumulator being configured to increment in response to a digital clock signal to thereby generate a free-running primary digital signal in accordance with the primary modulation signal; at least one secondary signal synthesizer disposed in parallel with the primary signal synthesizer, the at least one secondary signal synthesizer including at least one secondary frequency accumulator in series with a corresponding one of at least one secondary phase accumulator, the at least one secondary frequency accumulator being configured to generate at least one secondary digital modulation signal based on at least one secondary frequency, the at least one secondary phase accumulator being configured to increment in response to the digital clock signal to thereby generate a free-running at least one secondary digital signal in accordance with the at least one secondary digital modulation signal; and a switch element including a first switch input coupled to the primary signal synthesizer and at least one second switch input coupled to the at least one secondary signal synthesizer, the switch element being configured to select a switch output that provides either the primary digital signal or the at least one secondary digital signal based on a switch control input, a latter switch element output of the primary digital signal provided after the switch element output the at least one secondary digital signal being phase coherent with a former switch output of the primary digital signal provided before the switch element output the at least one secondary digital signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A coherent radar system comprising:
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an antenna system configured to radiate RF radar signals and receive ambient RF signals; a timing circuit configured to provide a digital clock signal; a transmitter coupled to the antenna system and configured to direct the RF radar signals into the antenna system; a receiver system coupled to the antenna system and configured to detect RF radar return signals in the ambient RF signals, the detected RF radar return signals corresponding to the radiated RF radar signals; and a digital local oscillator coupled to the transmitter system and the receiver system, the digital local oscillator being implemented as an integrated circuit device, the digital local oscillator including, a primary frequency accumulator configured to generate a primary digital modulation signal corresponding to a predetermined primary modulation format and a predetermined primary frequency, a primary phase accumulator coupled in series with an output of the primary frequency accumulator, the primary phase accumulator being configured to increment in response to the digital clock signal to thereby generate a free-running primary digital frequency signal in accordance with the primary digital modulation signal, at least one secondary frequency accumulator configured to generate at least one second digital modulation signal corresponding to at least one secondary frequency, at least one secondary phase accumulator coupled in series with the at least one secondary frequency accumulator, the at least one secondary phase accumulator being configured to increment in response to the digital clock signal to thereby generate a free-running at least one second digital frequency signal in accordance with at least one second digital modulation signal, and a switch element including a first switch input coupled to the primary phase accumulator and at least one second switch input coupled to the at least one secondary phase accumulator, the switch element being configured to provide a switch output that transmits either the free-running primary digital frequency signal or the free-running at least one second digital frequency signal based on a switch control input, a latter occurrence of the primary digital frequency signal provided after an occurrence of the at least one secondary digital frequency signal being phase coherent with a former occurrence of the primary digital frequency signal provided before the occurrence of the at least one secondary digital frequency signal, and a latter occurrence of the at least one secondary digital frequency signal provided after an occurrence of the primary digital frequency signal being phase coherent with a former occurrence of the at least one secondary digital frequency signal provided before the occurrence of the primary digital frequency signal. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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Specification