Static random access memory cell and devices using same

• US 7,952,912 B2
• Filed: 06/06/2008
• Issued: 05/31/2011
• Est. Priority Date: 06/06/2008
• Status: Expired due to Fees

• Current Assignee: Purdue Research Foundation (Purdue University)
• Original Assignee: Purdue Research Foundation (Purdue University)
• Inventors: Kulkarni, Jaydeep P., Roy, Kaushik
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US12/134,352
• Publication Number:
  US 20090303775A1
• Time in Patent Office: 1,089 Days
• Field of Search: 365/154, 365/156, 365/207, 365/230.05
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

A bit-cell may include a pair of cross-coupled inverters, a left bit-line, a right bit-line, a word-line and a write-line. The left bit-line may be coupled to a left inverter of the cross-coupled inverters via a left word-line transistor and a left write-line transistor. The right bit-line may be coupled to a right inverter of the cross-coupled inverters via a right word-line transistor and a right write-line transistor. The word-line may be coupled to the gates of the left and right word-line transistors and the write-line may be coupled to the gates of the left and right write-line transistors. A memory device may include a controller, an array of such bit-cells and a differential sensing buffers. Further, a computing device may include a processor and a memory device having the above bit-cells.

Claims

1. A bit-cell comprising

a pair of cross-coupled inverters in which a left inverter has an output coupled to an input of a right inverter and the right inverter has an output coupled to an input of the left inverter, the left inverter to store a left value at the output of the left inverter and the right inverter to store a right value at the output of the right inverter,

a left word-line transistor coupled between a left bit-line and the left inverter, and

a word-line coupled to a gate of the left word-line transistor, the word-line to turn-on the left word-line transistor to dynamically raise a switching threshold of the left inverter during a read operation only when the left value is a high value and the right value is a low value.

2. The bit-cell of claim 1, further comprising a right word-line transistor coupled between a right bit-line and the right inverter, wherein the word-line is further coupled to a gate of the right word-line transistor to turn-on the right word-line transistor during a read operation.

3. The bit-cell of claim 1, wherein

the left inverter comprises a pull-up transistor and two pull-down transistors, the pull-up transistor coupled between the output of the left inverter and a supply voltage and the two pull-down transistors coupled in series between the output of the left inverter and ground, and

the left word-line transistor is coupled to the left inverter at a biasing node between the two pull-down transistors.

4. The bit-cell of claim 1, further comprising a right word-line transistor, wherein

the left inverter comprises a left pull-up transistor and two left pull-down transistors, the left pull-up transistor coupled between the output of the left inverter and a supply voltage and the two left pull-down transistors coupled in series between the output of the left inverter and ground,

the left word-line transistor is coupled to the left inverter at a left biasing node between the two left pull-down transistors,

the right inverter comprises a right pull-up transistor and two right pull-down transistors, the right pull-up transistor coupled between the output of the right inverter and the supply voltage and the two right pull-down transistors coupled in series between the output of the right inverter and ground,

the right word-line transistor is coupled between a right bit-line and the right inverter at a right biasing node between the two right pull-down transistors, and

the word-line is further coupled to a gate of the right word-line transistor to turn-on the right word-line transistor during a read operation.

5. The bit-cell of claim 1, further comprising

a right word-line transistor coupled between a right bit-line and the right inverter and a gate of the right word-line transistor coupled to the word-line,

a left write-line transistor coupled between the left bit-line and the output of the left inverter,

a right write-line transistor coupled between the right bit-line and the output of the right inverter,

a write-line coupled to a gate of the left write-line transistor and a gate of the right write-line transistor to turn-on the left write-line transistor and the right write-line transistor during a write operation.

6. The bit-cell of claim 1, further comprising

a left write-line transistor coupled between the left bit-line and the output of the left inverter,

a write-line coupled to a gate of the left write-line transistor,

wherein, during a write operation, the word-line is to turn-on the left word-line transistor, the write-line is to turn-on the left write-line transistor, and the left word-line transistor and the left write-line transistor each provide a pull-down path when changing the left value of the left inverter from a high value to a low value.

7. A memory device, comprising a controller and a plurality of bit-cells coupled to the controller via a plurality of differential bit-lines and a plurality of word-lines, each bit-cell of the plurality of bit-cells comprising

a pair of cross-coupled inverters in which a left inverter has an output coupled to an input of a right inverter and the right inverter has an output coupled to an input of the left inverter, the left inverter to store a left value at the output of the left inverter and the right inverter to store a right value at the output of the right inverter,

a left word-line transistor coupled between the left inverter and a left bit-line of a differential bit-line of the plurality of bit-lines, a right word-line transistor coupled between the right inverter and a right bit-line of the differential bit-line,

a word-line of the plurality of word-lines coupled to a gate of the left word-line transistor and a gate of the right word-line transistor, wherein

in response to a read operation of a word associated with the word-line, the controller is to turn-on the left word-line transistor and the right word-line transistor which raise a switching threshold of at least one inverter of the pair of cross-coupled inverters.

8. The memory device of claim 7, further comprising a plurality of differential sensing buffers coupled to the plurality of bit-cells via the plurality of differential bit-lines, each differential sensing buffer to sense a differential data signal received via a differential bit-line of the plurality of differential bit-lines and generate an output signal indicative of the sensed differential data signal.

9. The memory device of claim 7, wherein

the left inverter comprises a pull-up transistor and two pull-down transistors, the pull-up transistor coupled between the output of the left inverter and a supply voltage and the two pull-down transistors coupled in series between the output of the left inverter and ground, and

the left word-line transistor is coupled to the left inverter at a biasing node between the two pull-down transistors.

10. The memory device of claim 7, wherein

the left inverter comprises a left pull-up transistor and two left pull-down transistors, the left pull-up transistor coupled between the output of the left inverter and a supply voltage and the two left pull-down transistors coupled in series between the output of the left inverter and ground,

the left word-line transistor is coupled to the left inverter at a left biasing node between the two left pull-down transistors,

the right inverter comprises a right pull-up transistor and two right pull-down transistor, the right pull-up transistor coupled between the output of the right inverter and the supply voltage and the two right pull-down transistors coupled in series between the output of the right inverter and ground.

11. The memory device of claim 7, wherein

the controller is further coupled to the plurality of bit-cells via a plurality of write-lines,

each bit-cell of the plurality of bit-cells further comprises

a left write-line transistor coupled between the left bit-line and the output of the left inverter,

a right write-line transistor coupled between the right bit-line and the output of the right inverter,

a write-line of the plurality of write-lines coupled to a gate of the left write-line transistor and a gate of the right write-line transistor, and

in response to a write operation, the controller is to activate the write-line to turn-on the left write-line transistor and the right write-line transistor.

12. The memory device of claim 7, wherein

the controller is further coupled to the plurality of bit-cells via a plurality of write-lines, and

each bit-cell of the plurality of bit-cells further comprises

a left write-line transistor coupled between the left bit-line and the output of the left inverter,

a right write-line transistor coupled between the right bit-line and the output of the right inverter,

a write-line of the plurality of write-lines coupled to a gate of the left write-line transistor and a gate of the right write-line transistor, and

in response to a write operation, the controller is to activate the word-line to turn-on the left word-line transistor and right word-line transistor and to activate the write-line to turn-on the left write-line transistor and the right write-line transistor, wherein the left word-line transistor and the left write-line transistor each provides a pull-down path when changing the left value of the left transistor from a high value to a low value.

13. A computing device, comprising

a processor to execute instructions,

a controller, and

a plurality of bit-cells to store instruction, the plurality of bit-cells coupled to the controller, wherein

a bit-cell of the plurality of bit-cells comprises a pair of cross-coupled inverters in which a left inverter has an output coupled to an input of a right inverter and the right inverter has an output coupled to an input of the left inverter, a left word-line transistor coupled between a left bit-line and the left inverter at a left biasing node of the left inverter, a left write-line transistor coupled between a left bit-line and the left inverter at the output of the left inverter, a word-line coupled to a gate of the left word-line transistor, and a write-line coupled to a gate of the left write-line transistor,

in response to a read operation involving the bit-cell, the controller is to activate the word-line to turn-on the left word-line transistor and to de-activate the write-line to turn-off the left write-line transistor, and

in response to a write operation involving the bit-cell, the controller is to activate the word-line to turn-on the left word-line transistor and to activate the write-line to turn-on the left write-line transistor.

14. The computing device of claim 13, wherein the left word-line transistor raises a switching threshold of the left inverter during the read operation.

15. The computing device of claim 14, wherein the bit-cell further comprises a right word-line transistor coupled between a right bit-line and the right inverter and a gate of the right word-line transistor is coupled to the word-line.

16. The computing device of claim 14, wherein

the left inverter comprises a pull-up transistor and two pull-down transistor, the pull-up transistor coupled between the output of the left inverter and a supply voltage and the two pull-down transistors coupled in series between the output of the left inverter and ground, and

the left word-line transistor is coupled to the left inverter at a biasing node between the two pull-down transistors.

17. The computing device of claim 14, wherein

the bit-cell further comprises a right word-line transistor,

the left inverter comprises a left pull-up transistor and two left pull-down transistors, the left pull-up transistor coupled between the output of the left inverter and a supply voltage and the two left pull-down transistors coupled in series between the output of the left inverter and ground,

the left word-line transistor is coupled to the left inverter at a left biasing node between the two left pull-down transistors,

the right inverter comprises a right pull-up transistor and two right pull-down transistors, the right pull-up transistor coupled between the output of the right inverter and the supply voltage and the two right pull-down transistors coupled in series between the output of the right inverter and ground, and

the right word-line transistor is coupled between a right bit-line and the right inverter at a right biasing node between the two right pull-down transistors and a gate of the right word-line transistor is coupled to the word-line.

18. The computing device of claim 14, wherein the bit-cell further comprises

a right word-line transistor coupled between a right bit-line and the right inverter and a gate of the right word-line transistor coupled to the word-line, and

a right write-line transistor coupled between the right bit-line and the output of the right inverter and a gate of the right write-line transistor coupled to the write-line.

19. The computing device of claim 14, wherein the left write-line transistor and the left word-line transistor each provide a pull-down path when changing the left value of the left transistor from a high value to a low value.