Apparatus and method for port polarity initialization in a shared I/O device

• US 7,953,074 B2
• Filed: 01/31/2005
• Issued: 05/31/2011
• Est. Priority Date: 01/21/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Design & Manufacturing Corp. (Broadcom, Inc.)
• Inventors: Khan, Asif, Pagan, Annette, Utley, Robert Haskell, Pekkala, Richard E., Pettey, Christopher J.
• Primary Examiner(s): Harper; Kevin C
• Assistant Examiner(s): Divecha; Nishant B
• Application Number:
  US11/048,393
• Publication Number:
  US 20050147117A1
• Time in Patent Office: 2,311 Days
• Field of Search: 370/351, 370/360, 370/362, 370/428
• US Class Current: 370/362
• CPC Class Codes: H04L 49/356 for storage area networks

Abstract

An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus includes a first plurality of I/O ports, a second I/O port, and a plurality of port initialization logic elements. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports routes transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. One of the plurality of port initialization logic elements is coupled to the second I/O port and remaining ones of the plurality of port initialization logic elements are each coupled to a corresponding one of the first plurality of I/O ports. The plurality of port initialization logic elements is configured to initialize corresponding links between each of the plurality of operating system domains and the switching apparatus, and between the first shared input/output endpoint and the switching apparatus, to support the transactions, where each of the plurality of port initialization logic elements automatically configures a corresponding polarity for each of the first plurality of I/O ports and the second I/O port, and where the corresponding polarity is in a default polarity prior to being configured.

Claims

1. A switching apparatus for sharing input/output endpoints, the switching apparatus comprising:

a first shared I/O endpoint, configured to request/complete first transactions for each of a plurality of operating system domains, said each of said plurality of operating system domains corresponding to a separate root complex;

a switch, comprising;

a first plurality of I/O ports, coupled to said plurality of operating system domains through a load-store fabric, each configured to route said first transactions between said plurality of operating system domains and said switch according to the PCI Express protocol;

a second I/O port, coupled to a first shared input/output endpoint, wherein said first shared input/output endpoint requests/completes said first transactions for each of said plurality of operating system domains, wherein each of said first transactions is associated with a corresponding one of said plurality of operating system domains according to a variant of said PCl Express protocol, said variant comprising encapsulating an OS domain header within a PCI Express transaction layer packet that is otherwise identical with a conventional PCI Express transaction layer packet, and wherein a particular OS domain header associates a particular transaction layer packet with a particular one of said plurality of operating system domains; and

a plurality of port initialization logic elements, one coupled to said second I/O port, and remaining ones each coupled to a corresponding one of said first plurality of I/O ports, configured to initialize corresponding links between each of said plurality of operating system domains and said switch, and between said first shared input/output endpoint and said switch, to support said first transactions, wherein each of said plurality of port initialization logic elements automatically configures a corresponding polarity for each of said first plurality of I/O ports and said second I/O port, and wherein said corresponding polarity is in a default polarity prior to being configured.

2. The switching apparatus as recited in claim 1, wherein said corresponding polarity comprises an upstream port.

3. The switching apparatus as recited in claim 1, wherein said corresponding polarity comprises a downstream port.

4. The switching apparatus as recited in claim 1, wherein said default polarity comprises a downstream port.

5. The switching apparatus as recited in claim 4, wherein said one of said plurality of port initialization logic elements configures said second I/O port as an upstream port upon occurrence of a port polarity event.

6. The switching apparatus as recited in claim 5, wherein said port polarity event comprises a programmable event.

7. The switching apparatus as recited in claim 6, wherein said programmable event comprises a timeout event, and wherein a time for said timeout event is provided in a register within said one of said plurality of port initialization logic elements.

8. The switching apparatus as recited in claim 6, wherein said programmable event comprises a counter event, and wherein a count for said counter event is provided in a register within said one of said plurality of port initialization logic elements.

9. The switching apparatus as recited in claim 1, wherein the switching apparatus routes said first transactions according to said PCI Express protocol that provides for routing of said transactions only for said single operating system domain, and wherein said first plurality of I/O ports communicates with said plurality of operating system domains according to said PCI Express protocol.

10. The switching apparatus as recited in claim 9, wherein said default polarity comprises a PCI Express downstream port.

11. The switching apparatus as recited in claim 1, further comprising:

core logic, coupled to said first plurality of I/O ports and said second I/O port, configured to route said first transactions between said first plurality of I/O ports and said second I/O port, wherein said core logic maps said each of said plurality of operating system domains to a corresponding root complex.

12. The switching apparatus as recited in claim 11, wherein said corresponding root complex is associated with one or more processing complexes, each comprising:

a processing core, configured to process data, wherein said processing core accesses a memory that is configured to store said data.

13. The switching apparatus as recited in claim 11, wherein said core logic is configured to associate each of said first transactions with a corresponding one of said plurality of operating system domains (OSDs), said corresponding one of said plurality of OSDs corresponding to one or more root complexes.

14. The switching apparatus as recited in claim 1, wherein said corresponding polarity is configured without any intervention by system software.

15. The switching apparatus as recited in claim 14, wherein said system software comprises an operating system, a basic input/output system (BIOS), a configuration application, or a management application.

16. The switching apparatus as recited in claim 1, wherein the switching apparatus is incorporated into a root complex.

17. The switching apparatus as recited in claim 1, wherein the switching apparatus is incorporated into said first shared input/output endpoint.

18. The switching apparatus as recited in claim 1, wherein the switching apparatus is incorporated into a second input/output endpoint.

19. A shared input/output (I/O) switching mechanism, comprising:

a first shared I/O endpoint, configured to request/complete first transactions for each of a plurality of operating system domains, said each of said plurality of operating system domains corresponding to a separate root complex;

a switch, comprising;

a first plurality of I/O ports, coupled to a said plurality of operating system domains through a load-store fabric, each configured to route first transactions between said plurality of operating system domains and said switch according to a the PCI Express protocol;

a second I/O port, coupled to said first shared input/output endpoint;

core logic, coupled to said first plurality of I/O ports and said second I/O port, configured to route said first transactions between said first plurality of I/O ports and said second I/O port, wherein said core logic maps said each of said plurality of operating system domains to a corresponding root complex, and wherein said each of said first transactions is associated with a corresponding one of said plurality of operating system domains according to a variant of said PCI Express protocol, and wherein said variant comprises encapsulating an OS domain header within a PCI Express transaction layer packet that is otherwise identical with a conventional PCI Express transaction layer packet, and wherein a particular OS domain header associates a particular PCI Express transaction layer packet with a particular one of said plurality of operating system domains; and

a plurality of port initialization logic elements, one coupled to said second I/O port, and remaining ones each coupled to a corresponding one of said first plurality of I/O ports, configured to initialize corresponding links between said each of said plurality of operating system domains and the switching mechanism, and between said first shared input/output endpoint and said switch, to support said first transactions, wherein each of said plurality of port initialization logic elements automatically configures a corresponding polarity for each of said first plurality of I/O ports and said second I/O port, and wherein said corresponding polarity is in a default polarity prior to being configured.

20. The switching mechanism as recited in claim 19, wherein said corresponding polarity comprises an upstream port or a downstream port, and wherein said default polarity comprises said downstream port.

21. The switching mechanism as recited in claim 20 wherein said one of said plurality of port initialization logic elements configures said second I/O port as said upstream port upon occurrence of a port polarity event.

22. The switching mechanism as recited in claim 21, wherein said port polarity event comprises a programmable event.

23. The switching mechanism as recited in claim 22, wherein said programmable event comprises a timeout event, and wherein a time for said timeout event is provided in a register within said one of said plurality of port initialization logic elements.

24. The switching mechanism as recited in claim 22, wherein said programmable event comprises a counter event, and wherein a count for said counter event is provided in a register within said one of said plurality of port initialization logic elements.

25. The switching mechanism as recited in claim 19, wherein said first plurality of I/O ports communicates with said plurality of operating system domains according to said PCI Express protocol.

26. The switching mechanism as recited in claim 25, wherein said default polarity comprises a PCI Express downstream port.

27. The switching mechanism as recited in claim 19, wherein said corresponding root complex is associated with one or more processing complexes, each comprising:

a processing core, configured to process data, wherein said processing core accesses a memory that is configured to store said data.

28. The switching mechanism as recited in claim 19, wherein said core logic is configured to associate each of said first transactions with a corresponding one of said plurality of operating system domains (OSDs), said corresponding one of said plurality of OSDs corresponding to one or more root complexes.

29. The switching mechanism as recited in claim 19, wherein said corresponding polarity is configured without any intervention by system software.

30. The switching mechanism as recited in claim 19, wherein the switching mechanism is incorporated into a root complex.

31. The switching mechanism as recited in claim 19, wherein the switching mechanism is incorporated into said first shared input/output endpoint.

32. The switching mechanism as recited in claim 19, wherein the switching mechanism is incorporated into a second input/output endpoint.

33. A method for interconnecting independent operating system domains to a shared I/O endpoint within a load-store fabric, comprising:

providing separate root complexes that correspond to the independent operating system domains;

via first ports, first communicating with each of the independent operating system domains according to the PCI Express protocol;

via a second port, second communicating with the shared I/O endpoint according to a variant of the PCI Express protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains, wherein said second communicating comprises encapsulating an OS domain header within a PCI Express transaction layer packet that is otherwise identical with a conventional PCI Express transaction layer packet, and wherein a particular OS domain header associates the PCI Express transaction layer packet with the corresponding one of the independent operating system domains; and

initializing links between each of the independent operating system domains and the first ports, and between the shared I/O endpoint and the second port, wherein said initializing comprises;

automatically configuring a corresponding polarity for each of the first ports and the second port, wherein the corresponding polarity is in a default polarity prior to said configuring.

34. The method as recited in claim 33, wherein said configuring comprises:

first establishing the default polarity as a downstream port; and

automatically second establishing the corresponding polarity as an upstream port.

35. The method as recited in claim 34, wherein said automatically second establishing comprises:

changing the corresponding polarity for the second I/O port to the upstream port upon occurrence of a port polarity event.

36. The method as recited in claim 35, wherein the port polarity event comprises a programmable event.

37. The method as recited in claim 36, wherein the programmable event comprises a timeout event, and wherein a time for the timeout event is provided in a register within one of a plurality of port initialization logic elements that is coupled to the second I/O port.

38. The method as recited in claim 36, wherein the programmable event comprises a counter event, and wherein a count for the counter event is provided in a register within one of a plurality of port initialization logic elements that is coupled to the second I/O port.

39. The method as recited in claim 33, wherein the default polarity comprises a PCI Express downstream port.

40. The method as recited in claim 33, wherein each of the independent operating system domains is coupled to a corresponding one of the separate root complexes, and wherein the corresponding one of the separate root complexes is associated with one or more processing complexes, each comprising:

a processing core, configured to process data, wherein the processing core accesses a memory that is configured to store said data.

41. The method as recited in claim 33, wherein said automatically configuring of the corresponding polarity is accomplished without any intervention by system software.

42. The method as recited in claim 41, wherein the system software comprises an operating system, a basic input/output systems (BIOS), a configuration application, or a management application.

43. The method as recited in claim 33, wherein the first and second ports are incorporated into one of the separate root complexes.

44. The method as recited in claim 33, wherein the first and second ports are incorporated into the shared I/O endpoint.

45. The method as recited in claim 33, wherein the first and second ports are incorporated into a different I/O endpoint.

46. A switching apparatus, comprising:

a first port, coupled to a first root complex, configured to route first transactions between said first root complex and the switching apparatus according to the PCI Express protocol;

a second port, coupled to a second root complex, configured to route second transactions between said second root complex and the switching apparatus according to said PCI Express protocol;

a port initialization logic element, coupled to said first and second ports, configured to initialize links between said first and second root complexes and the switching apparatus, to support said first and second transactions, wherein said port initialization logic element automatically configures a corresponding polarity for each of said first and second ports, and wherein said corresponding polarity is in a default polarity prior to being configured;

wherein the switching apparatus routes said first and second transactions to a shared I/O device according to a variant said PCI Express protocol, and wherein the switching apparatus communicates with said shared I/O device according to said variant of said PCI Express protocol by encapsulating an OS domain header within a PCI Express transaction layer packet that is otherwise identical with a conventional PCI Express transaction layer packet, and wherein a particular OS domain header associates a particular PCI Express transaction layer packet with a particular one of a plurality of operating system domains.

47. The switching apparatus as recited in claim 46, wherein said corresponding polarity comprises an upstream port.

48. The switching apparatus as recited in claim 46, wherein said corresponding polarity comprises a downstream port.

49. The switching apparatus as recited in claim 46, wherein said default polarity comprises a downstream port.

50. The switching apparatus as recited in claim 49, wherein said port initialization logic element configures said port as an upstream port upon occurrence of a port polarity event.

51. The switching apparatus as recited in claim 49, wherein said port polarity event comprises a programmable event.

52. The switching apparatus as recited in claim 51, wherein said programmable event comprises a timeout event, and wherein a time for said timeout event is provided in a register within said port initialization logic element.

53. The switching apparatus as recited in claim 51, wherein said programmable event comprises a counter event, and wherein a count for said counter event is provided in a register within said port initialization logic element.

54. The switching apparatus as recited in claim 46, wherein said protocol comprises a PCI Express protocol and wherein said default polarity comprises a PCI Express downstream port.

55. The switching apparatus as recited in claim 46, wherein said corresponding polarity is configured without any intervention by system software.

56. The switching apparatus as recited in claim 55, wherein said system software comprises an operating system, a basic input/output system (BIOS), a configuration application, or a management application.

57. The switching apparatus as recited in claim 46, wherein the switching apparatus is incorporated into a root complex.

58. The switching apparatus as recited in claim 46, wherein the switching apparatus is incorporated into an input/output endpoint.