Use of differential pair as single-ended data paths to transport low speed data

• US 7,953,162 B2
• Filed: 11/17/2006
• Issued: 05/31/2011
• Est. Priority Date: 11/17/2006
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Shetty, Naresh B.
• Primary Examiner(s): Fan; Chieh M
• Assistant Examiner(s): Garcia; Santiago
• Application Number:
  US11/601,070
• Publication Number:
  US 20080117994A1
• Time in Patent Office: 1,656 Days
• Field of Search: 375/257
• US Class Current: 375/257
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/45 using electronic distributors
• CPC Class Codes: H04W 52/52 using AGC [Automatic Gain Control] circuits or amplifiers

Abstract

Provided herein are systems and methods for transmitting signals across a pair of wires. In accordance with specific embodiments, a differential signal is transmitted across the pair of wires during one period of time, and two single-ended signals are transmitted across the same pair of wires during another period of time. Low voltage differential signaling (LVDS) can be used to transmit the differential signal across the pair of wires. In contrast, non-differential signaling can be used to transfer the two singled-ended signals across the same pair of wires.

Claims

1. A method for transmitting signals across a pair of wires, comprising:

(a) transmitting differential signals across the pair of wires during a period of time when a device is in an active mode, the differential signals being transmitted across the pair of wires comprising high speed video signals, and the differential signals being transmitted across the pair of wires also comprising low speed serial clock (SCL) and serial data (SDA) signals embedded with the high speed video signals; and

(b) transmitting two single-ended signals across the same pair of wires during another period of time when the device is in a sleep or standby mode, neither of the two single-ended signals comprising the high speed video signals, one of the two single-ended signals being transmitted across one of the wires comprising the low speed serial clock (SCL) signal, and the other one of the two single-ended signals being transmitted across the other one of the wires comprising the low speed serial data (SDA) signal.

2. The method of claim 1, wherein:

step (a) includes using low voltage differential signaling (LVDS) to transmit the differential signals across the pair of wires; and

step (b) includes using non-differential signaling to transfer the two singled-ended signals across the same pair of wires.

3. The method of claim 1, wherein the pair of wires comprises a twisted pair.

4. The method of claim 1, wherein the pair of wires comprises a pair of conductive traces.

5. The method of claim 1, wherein the sleep or standby mode is a reduced power mode as compared to the active mode.

18. The method of claim 1, further comprising:

when the device is in the sleep or standby mode, disabling at least some circuitry that is used for transmitting differential signals across the pair of wires, to thereby reduce power consumption.

21. The method of claim 1, wherein:

the high speed video signals are transmitted at a first speed that is at least 1 MHz; and

the low speed serial clock (SCL) and serial data (SDA) signals are transmitted at a lower speed than the first speed, the lower speed being no more than 400 KHz.

24. The method of claim 1, further comprising:

monitoring for at least one of a data enable signal (DATAEN) and a processor clock signal (PCLK); and

selecting a mode of operation, based on results of the monitoring, the mode of operation being one of the active mode and the sleep or standby mode.

6. A method for reducing power consumption in a battery powered mobile device that has a first mode and a second mode, the method comprising:

(a) using low voltage differential signaling (LVDS) to transfer high speed video signals, and low speed serial clock (SCL) and serial data (SDA) signals embedded with the high speed video signals, across a pair of wires, when the device is in the first mode; and

(b) using non-differential signaling to transfer the low speed serial clock (SCL) signal and the low speed serial data (SDA) signals, but not the high speed video signals, across the same pair of wires, when the device is in the second mode;

wherein when the device is in the second mode, the low speed serial clock (SCL) signal is transferred using non-differential signaling across one of the pair of wires, and the low speed serial data (SDA) signal is transferred using non-differential signaling across the other one of the pair of wires.

7. The method of claim 6, wherein:

step (a) includes using the pair of wires as a single differential pair, when the device is in the first mode; and

step (b) includes using the pair of wires as two separate serial lines, when the device is in the second mode.

8. The method of claim 6, wherein:

the first mode is an active mode; and

the second mode is a sleep or standby mode.

9. The method of claim 6, wherein the second mode is a reduced power mode as compared to the first mode.

10. The method of claim 6, wherein:

the high speed video signals are to be transferred at a first speed that is at least 1 MHz; and

the low speed serial clock (SCL) and serial data (SDA) signals are to be transferred at a lower speed than the first speed, the lower speed being no more than 400 KHz.

25. The method of claim 6, further comprising:

monitoring for at least one of a data enable signal (DATAEN) and a processor clock signal (PCLK); and

selecting one of the first and second modes based on results of the monitoring.

26. The system of claim 9, further comprising a mode controller configured to:

monitor for at least one of a data enable signal (DATAEN) and a processor clock signal (PCLK); and

select one of the first and second modes based on whether the at least one of the data enable signal (DATAEN) and the processor clock signal (PCLK) is/are detected.

11. A system, comprising:

a transmitter configured to transmit high speed video signals and low speed serial clock (SCL) and serial data (SDA) signals, the transmitter including a pair of outputs; and

a receiver including a pair of inputs;

wherein the pair of outputs of the transmitter are configured to be connected, by a pair of wires, to the pair of inputs of the receiver;

wherein the transmitter, when in a first mode, outputs differential signals at the two outputs to transmit across the two wires to the two inputs of the receiver, the differential signals including the high speed video signals and the low speed serial clock (SCL) and serial data (SDA) signals embedded with the high speed video signals; and

wherein the transmitter, when in a second mode, outputs two single-ended signals, one at each of the two outputs, to transmit across the same two wires to the two inputs of the receiver, one of the two single-ended signals including the low speed serial clock (SCL) signal, the other one of the two single-ended signals including the low speed serial data (SDA) signal, and neither of the two single-ended signals including the high speed video signals.

12. The system of claim 11, wherein:

at any given time, the receiver can be in one of the first mode and the second mode;

the receiver treats signals received at its two inputs as a differential signal, when the receiver is in the first mode; and

the receiver treats signals received at its two inputs as two single-ended signals when the receiver is in the second mode.

13. The system of claim 11, wherein:

the first mode is an active mode; and

the second mode is a sleep or standby mode.

14. The system of claim 11, wherein the second mode is a reduced power mode as compared to the first mode.

15. The system of claim 11, wherein the transmitter includes a pair of switches that enable the low speed serial clock (SCL) and serial data (SDA) signals to be transmitted either as an embedded portion of the differential signals across the pair of wires, or as two separate single-ended signals across the same pair of wires.

16. The system of claim 11, wherein:

the transmitter includes a serializer and an output stage that produces the differential signals based on an output of the serializer; and

the receiver includes an input stage that produces single-ended signals based on the differential signals received at the two inputs of the receiver, and a deserializer that receives an output of the input stage.

19. The system of claim 11, wherein:

the transmitter is part of a first transceiver of the system; and

the receiver is part of a second transceiver of the system.

22. The system of claim 11, wherein:

the high speed video signals are transmitted at a first speed that is at least 1 MHz; and

the low speed serial clock (SCL) and serial data (SDA) signals are transmitted at a lower speed than the first speed, the lower speed being no more than 400 KHz.

17. A system for transmitting signals across a pair of wires, comprising:

means for transmitting differential signals across the pair of wires during a period of time when the system is in an active mode, the differential signals comprising high speed video signals and low speed serial clock (SCL) and serial data (SDA) signals embedded with the high speed video signals; and

means for transmitting two single-ended signals across the same pair of wires during another period of time when the system is in a sleep or standby mode, neither of the two single-ended signals comprising the high speed video signals, one of the two single-ended signals comprising the low speed serial clock (SCL) signal, and the other one of the two single-ended signals comprising the low speed serial data (SDA) signal.

20. The system of claim 17, wherein when the system is in the sleep or standby mode, at least some circuitry, used for transmitting differential signals across the pair of wires, is disabled to thereby reduce power consumption.

23. The system of claim 17, wherein:

the high speed video signals are transmitted at a first speed that is at least 1 MHz; and

the low speed serial clock (SCL) and serial data (SDA) signals are transmitted at a lower speed than the first speed, the lower speed being no more than 400 KHz.

27. The system of claim 17, further comprising:

means for monitoring for at least one of a data enable signal (DATAEN) and a processor clock signal (PCLK); and

means for selecting one of the active mode and the sleep or standby mode based on whether the at least one of the data enable signal (DATAEN) and the processor clock signal (PCLK) is/are detected.