High endurance non-volatile memory devices

• US 7,953,931 B2
• Filed: 02/21/2008
• Issued: 05/31/2011
• Est. Priority Date: 08/04/1999
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Lee, Charles C., Chow, David Q., Ma, Abraham Chih-Kang, Yu, I-Kang
• Primary Examiner(s): Thomas; Shane M
• Assistant Examiner(s): Birkhimer; Christopher D
• Application Number:
  US12/035,398
• Publication Number:
  US 20080209112A1
• Time in Patent Office: 1,195 Days
• Field of Search: None
• US Class Current: 711/117
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Claims

1. A method of managing data transfer operations in a high endurance non-volatile memory device (NVMD) adapted to a host computer system, the NVMD comprises a volatile memory as a data cache subsystem and at least one non-volatile memory module as a data storage of the host, the method comprises:

receiving a data transfer request including a logical sector address (LSA) of data to be transferred from the host computer system;

determining whether a ‘

cache-hit’

or a ‘

cache-miss’

status in the data cache subsystem according to an index and a tag derived from the received LSA, the ‘

cache-hit’

status represents a ‘

cache-hit’

cache line contains relevant data;

determining whether the data transfer request is a read or a write operation;

when the read operation and the ‘

cache-hit’

are determined, retrieving requested data from the ‘

cache-hit’

cache line and sending to the host; and

updating a cache usage status;

when the read operation and the ‘

cache-miss’

are determined, loading the request data from the at least one non-volatile memory module based on the received LSA to a least-recently used (LRU) cache line in the data cache subsystem;

sending the requested data to the host; and

updating a cache usage status;

when the write operation and the ‘

cache-hit’

are determined, writing incoming data to ‘

cache-hit’

cache line;

updating the cache usage status; and

storing the incoming data into the at least one non-volatile memory module according to the received LSA; and

when the write operation and the ‘

cache-miss’

are determined, writing the incoming data to the LRU cache line;

updating the cache usage status; and

storing the incoming data into the at least one non-volatile memory module according to the received LSA;

wherein the at least one non-volatile memory module includes Single-Level Cell flash memory (SLC) and Multi-Level Cell flash memory (MLC) and said storing the incoming data into the at least one non-volatile memory module according to the received LSA further comprises;

if SLC data programming rules allow, storing the incoming data to a block corresponding to the physical address in the SLC, otherwise storing the incoming data to a new available SLC block;

when the SLC has been used up to its capacity, a lowest hit block in the SLC is copied to a new MLC block for reuse, the new MLC block is allocated according to a selection process using a probability density function along with a pseudo random number generator.

2. The method of claim 1, wherein the received LSA corresponds to one physical address either in the SLC or in the MLC.

3. The method of claim 1, wherein the SLC and the MLC are arranged in a hierarchical scheme such that the SLC is a buffer between the data cache subsystem and the MLC and total capacity of the NVMD comprises a combined capacity of the SLC and the MLC.

4. The method of claim 1, wherein the cache usage status includes data validity, least-recently use, number of write hits.

5. A method of initializing a cache subsystem of a non-volatile memory device (NVMD) having first and second types of non-volatile memory (NVM) arranged in a hierarchical scheme with the first type of NVM as a buffer between the cache subsystem and the second type of NVM, the method comprises:

(a) receiving a power on or reset signal in the NVMD;

(b) retrieving tag, index, set number and number-of-hits flag from spare area of first page of a block in the first type of NVM;

(c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number;

(d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and

repeating (a)-(d) for another block of the first type of NVM until there are no more blocks.

6. The method of claim 5, wherein the first type of NVM is single-level cell flash memory while the second type is multi-level cell flash memory.