Secured coprocessor comprising an event detection circuit
First Claim
1. A method for securing an execution of a command by a coprocessor, the method comprising:
- putting the coprocessor into an error mode by default as soon as the execution of the command begins;
monitoring the execution of the command so as to detect any execution error;
lifting the error mode at an end of the execution of the command if no error has been detected in the execution of the command, or otherwise maintaining the error mode; and
declaring the error mode to an outside of the coprocessor if a particular event happens while the coprocessor is in the error mode.
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Accused Products
Abstract
A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.
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Citations
13 Claims
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1. A method for securing an execution of a command by a coprocessor, the method comprising:
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putting the coprocessor into an error mode by default as soon as the execution of the command begins; monitoring the execution of the command so as to detect any execution error; lifting the error mode at an end of the execution of the command if no error has been detected in the execution of the command, or otherwise maintaining the error mode; and declaring the error mode to an outside of the coprocessor if a particular event happens while the coprocessor is in the error mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus for securing an execution of a command by a coprocessor, the apparatus comprising:
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means for putting the coprocessor into an error mode by default at a beginning of an execution of the command; means for monitoring the execution of the command to detect an execution error; means for lifting the error mode at an end of the execution of the command if no execution error has been detected and for otherwise maintaining the error mode; and means for declaring the error mode externally to the coprocessor if a particular event is detected while the coprocessor is in the error mode. - View Dependent Claims (12, 13)
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Specification