Apparatus and method for reducing interference

• US 7,955,886 B2
• Filed: 03/30/2005
• Issued: 06/07/2011
• Est. Priority Date: 03/30/2005
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Marques, Augusto Manuel
• Primary Examiner(s): MANDALA, MICHELLE
• Application Number:
  US11/094,833
• Publication Number:
  US 20060220778A1
• Time in Patent Office: 2,260 Days
• Field of Search: 438/10, 438/14, 438/17, 438/57, 438/66, 438/73, 438/199, 257/48, 257/108, 257/421, 257/531, 257/E29.167, 257/E21.022, 257/E21.521
• US Class Current: 438/57
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 27/346 Preventing or reducing leakage fields using magnetic shields H01F27/36; using auxiliary windings H01F27/38
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.

Claims

1. A method of minimizing interference between RF circuitry and digital circuitry on an integrated circuit comprising:

forming an inductance on the integrated circuit using first and second conductive loops coupled together, the first and second conductive loops defining a first axis extending through the first and second conductive loops and defining a second axis perpendicular to the first axis;

configuring the first and second conductive loops such that current flows in opposite directions in the first and second loops to at least partially cancel magnetic fields generated from the loops, and such that magnetic cancellation is maximized at locations along the second axis; and

configuring relative positions of the inductance and circuitry on the integrated circuit to achieve a desired amount of magnetic cancellation.

2. The method of claim 1, wherein the first and second conductive loops are coupled together in series.

3. The method of claim 1, wherein the first and second conductive loops are coupled together in parallel.

4. The method of claim 1, wherein the second axis is located at approximately the mid point between the first and second conductive loops.

5. A method of minimizing interference on an integrated circuit comprising:

forming an inductance on the integrated circuit using a plurality of conductive loops configured to at least partially cancel magnetic fields generated from the loops; and

configuring relative positions of the inductance and other circuitry on the integrated circuit to achieve a desired amount of magnetic cancellation, wherein the plurality of conductive loops are configured such that magnetic cancellation is maximized in a first direction extending from the inductance.

6. The method of claim 5, further comprising configuring the relative position of the other circuitry on the integrated circuit such that the other circuitry lies generally in the first direction from the inductance.

7. The method of claim 5, further comprising positioning a first circuit on the integrated circuit at a location that is generally positioned in the first direction, relative to the inductance, to minimize interference between the first circuit and the inductance.

8. The method of claim 5, wherein the inductance is part of voltage controlled oscillator circuitry formed on the integrated circuit.

9. The method of claim 8, wherein the other circuitry on the integrated circuit comprises digital circuitry.

10. An integrated circuit, comprising:

an inductance formed using a plurality of conductive loops adapted to at least partially cancel magnetic fields generated from the loops,

wherein relative positions of the inductance and other circuitry on the integrated circuit are adapted so as to achieve a desired amount of magnetic cancellation, and

wherein the plurality of conductive loops are adapted such that magnetic cancellation is maximized in a first direction extending from the inductance.

11. The integrated circuit of claim 10, wherein the other circuitry on the integrated circuit is formed such that the other circuitry lies generally in the first direction from the inductance.

12. The integrated circuit of claim 10, comprising a first circuit on the integrated circuit at a location that is generally positioned in the first direction, relative to the inductance, to minimize interference between the first circuit and the inductance.

13. The integrated circuit of claim 10, comprising radio-frequency circuitry.

14. The integrated circuit of claim 10, wherein the radio-frequency circuitry comprises transceiver circuitry.

15. The integrated circuit of claim 10, wherein the radio-frequency circuitry comprises receiver circuitry.

16. The integrated circuit of claim 10, wherein the radio-frequency circuitry comprises transmitter circuitry.

17. The integrated circuit of claim 10, comprising voltage controlled oscillator circuitry.

18. The integrated circuit of claim 17, wherein the inductance is part of the voltage controlled oscillator circuitry.

19. The integrated circuit of claim 17, wherein the voltage controlled oscillator circuitry is located within the integrated circuit so as to reduce interference within the integrated circuit.

20. The integrated circuit of claim 17, wherein the voltage controlled oscillator circuitry is positioned within the integrated circuit so as to reduce interference between the other circuitry on the integrated circuit and the inductance.