Method of manufacturing a semiconductor device

• US 7,955,912 B2
• Filed: 06/25/2010
• Issued: 06/07/2011
• Est. Priority Date: 08/11/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuma, Hideto, Uehara, Ichiro
• Primary Examiner(s): Booth; Richard A.
• Application Number:
  US12/823,175
• Publication Number:
  US 20100261320A1
• Time in Patent Office: 347 Days
• Field of Search: 438151-166, 257/E21.561
• US Class Current: 438/155
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: Y10S 438/949 Energy beam treating radiation resist on semiconductor

Abstract

Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming an insulating film over a first semiconductor of a transistor and a second semiconductor for a capacitor to be electrically connected to the transistor;

forming a conductive film over the first semiconductor and the second semiconductor with the insulating film interposed therebetween;

forming a resist pattern over the conductive film by performing a light exposure using a photomask;

patterning the conductive film to form at least a first gate electrode over the first semiconductor and a second electrode over the second semiconductor by using the resist pattern, the second electrode including a first portion and a second portion where the second portion is thicker than the first portion;

introducing a first impurity element into the first semiconductor with the first gate electrode as a mask to form a pair of impurity regions with a channel forming region therebetween; and

introducing a second impurity element into the second semiconductor with the second electrode as a mask wherein a portion of the second impurity element penetrates the first portion of the second electrode to form an impurity region in the second semiconductor so as to overlap with the first portion of the second electrode,

wherein the photomask comprises a first pattern which substantially blocks light and a second pattern which blocks light only partly, the second pattern corresponding to the first portion of the second electrode.

2. The method according to claim 1 wherein the second pattern of the photomask has a diffraction grating pattern.

3. The method according to claim 1 wherein the second pattern of the photomask has a translucent film.

4. The method according to claim 1 wherein the first semiconductor is a first semiconductor film, and the second semiconductor is a second semiconductor film, both formed on an insulating surface.

5. The method according to claim 1 wherein the step of introducing the first impurity element is performed simultaneously as the step of introducing the second impurity element.

6. The method according to claim 1 wherein the first impurity element is a same element as the second impurity element.

7. A method of manufacturing a semiconductor device, the method comprising:

forming an insulating film over a first semiconductor of a transistor and a second semiconductor for a capacitor to be electrically connected to the transistor

forming a conductive film over the first semiconductor and the second semiconductor with the insulating film interposed therebetween;

forming a resist pattern over the conductive film by performing a light exposure using a reticle;

patterning the conductive film to form at least a first gate electrode over the first semiconductor and a second electrode over the second semiconductor by using the resist pattern, the second electrode including a first portion and a second portion where the second portion is thicker than the first portion;

introducing a first impurity element into the first semiconductor with the first gate electrode as a mask to form a pair of impurity regions with a channel forming region therebetween; and

introducing a second impurity element into the second semiconductor with the second electrode as a mask wherein a portion of the second impurity element penetrates the first portion of the second electrode to form an impurity region in the second semiconductor so as to overlap with the first portion of the second electrode,

wherein the reticle comprises a first pattern which substantially blocks light and a second pattern which blocks light only partly, the second pattern corresponding to the first portion of the second electrode.

8. The method according to claim 7 wherein the second pattern of the reticle has a diffraction grating pattern.

9. The method according to claim 7 wherein the second pattern of the reticle has a translucent film.

10. The method according to claim 7 wherein the first semiconductor is a first semiconductor film, and the second semiconductor is a second semiconductor film, both formed on an insulating surface.

11. The method according to claim 7 wherein the step of introducing the first impurity element is performed simultaneously as the step of introducing the second impurity element.

12. The method according to claim 7 wherein the first impurity element is a same element as the second impurity element.

13. A method of manufacturing a semiconductor device, the method comprising:

forming, over a substrate, an insulating film over a first semiconductor film of a transistor and a second semiconductor film for a capacitor to be electrically connected to the transistor

forming a conductive film over the first semiconductor film and the second semiconductor film with the insulating film interposed therebetween;

forming a resist pattern over the conductive film by performing a light exposure using a photomask;

patterning the conductive film to form at least a first gate electrode over the first semiconductor film and a second electrode over the second semiconductor film by using the resist pattern, the second electrode including a first portion and a second portion where the second portion is thicker than the first portion;

introducing a first impurity element into the first semiconductor film with the first gate electrode as a mask to form a pair of impurity regions with a channel forming region therebetween;

introducing a second impurity element into the second semiconductor film with the second electrode as a mask wherein a portion of the second impurity element penetrates the first portion of the second electrode to form an impurity region in the second semiconductor film so as to overlap with the first portion of the second electrode; and

forming a pixel electrode over the substrate to be electrically connected to the transistor,

wherein the photomask comprises a first pattern which substantially blocks light and a second pattern which blocks light only partly, the second pattern corresponding to the first portion of the second electrode.

14. The method according to claim 13 wherein the second pattern of the photomask has a diffraction grating pattern.

15. The method according to claim 13 wherein the second pattern of the photomask has a translucent film.

16. The method according to claim 13 wherein the step of introducing the first impurity element is performed simultaneously as the step of introducing the second impurity element.

17. The method according to claim 13 wherein the first impurity element is a same element as the second impurity element.

18. A method of manufacturing a semiconductor device, the method comprising:

forming, over a substrate, an insulating film over a first semiconductor film of a transistor and a second semiconductor film for a capacitor to be electrically connected to the transistor

forming a conductive film over the first semiconductor film and the second semiconductor film with the insulating film interposed therebetween;

forming a resist pattern over the conductive film by performing a light exposure using a photomask;

patterning the conductive film to form at least a first gate electrode over the first semiconductor film and a second electrode over the second semiconductor film by using the resist pattern, the second electrode including a first portion and a second portion where the second portion is thicker than the first portion;

introducing a first impurity element into the first semiconductor film with the first gate electrode as a mask to form a pair of impurity regions with a channel forming region therebetween;

introducing a second impurity element into the second semiconductor film with the second electrode as a mask wherein a portion of the second impurity element penetrates the first portion of the second electrode to form an impurity region in the second semiconductor film so as to overlap with the first portion of the second electrode; and

forming a pixel electrode over the substrate to be electrically connected to the transistor,

wherein the photomask comprises a first pattern which substantially blocks light and a second pattern which blocks light only partly, the second pattern corresponding to the first portion of the second electrode.

19. The method according to claim 18 wherein the second pattern of the photomask has a diffraction grating pattern.

20. The method according to claim 18 wherein the second pattern of the photomask has a translucent film.

21. The method according to claim 18 wherein the step of introducing the first impurity element is performed simultaneously as the step of introducing the second impurity element.

22. The method according to claim 18 wherein the first impurity element is a same element as the second impurity element.