Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

• US 7,955,955 B2
• Filed: 05/10/2007
• Issued: 06/07/2011
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Melville, Ian D. W., Liu, Xiao Hu, Farooq, Mukta G., Hannon, Robert, Shaw, Thomas M., Lane, Michael W.
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US11/746,684
• Publication Number:
  US 20080277765A1
• Time in Patent Office: 1,489 Days
• Field of Search: 438/33, 438/68, 438/113, 438/114, 438/458, 438/460, 438/462, 438/465
• US Class Current: 438/465
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/18301 being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Claims

1. A method of forming a semiconductor product comprising a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip with said semiconductor substrate having a top surface and a perimeter;

an active device (FEOL) layer on said top surface, a BEOL layer on top of said FEOL layer, and a barrier formed in said chip within said perimeter;

comprising

the step of cutting a trench extending down through said top surface of said semiconductor product, but extending only partially down into said substrate between said barrier and the outermost of said perimeter, prior to performing the following steps;

forming a blanket underfill layer over said product completely covering said semiconductor product and completely filling said trench, and

dicing said semiconductor product into chips.

2. A method of forming a semiconductor product comprising a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip with said semiconductor substrate having a top surface and a perimeter;

and a crack stop barrier formed in said chip within said perimeter, and with an active device layer and an interconnection structure above said substrate;

comprising

the step of cutting a trench extending down through said top surface of said semiconductor product, but extending only partially down into said active device layer or said substrate between said crack stop barrier and the outermost of said perimeter, prior to performing the following steps;

forming a blanket underfill layer over said product completely covering said interconnection structure and completely filling said trench, and

dicing said semiconductor product into chips.

3. The method of claim 2 including:

spacing said trench laterally with respect to said top surface of said substrate from said barrier, and

spacing said trench from said diced edge of said chip.

4. The method of claim 3 wherein said underfill layer comprises an organic polymer filled with silica beads.

5. The method of claim 2 wherein a plurality of trenches are formed nested one inside another in a sequence of trenches of increasing lateral dimensions are formed cut into said top surface of said semiconductor chip surrounding said barrier, between said perimeter and said barrier.

6. The method of claim 5 wherein said underfill layer comprises an organic polymer filled with silica beads.

7. The method of claim 2 wherein said trench is slanted at an angle with respect to said top surface.

8. The method of claim 7 wherein said underfill layer comprises an organic polymer filled with silica beads.

9. The method of claim 2 wherein said step of forming said trench and said step of forming said underfill layer are performed prior to said step of dicing said semiconductor product into chips.

10. The method of claim 9 wherein said underfill layer comprises an organic polymer filled with silica beads.

11. The semiconductor product of claim 2 comprising:

forming a semiconductor device in said semiconductor product; and

forming an interconnection structure above said active device layer containing dielectric layers, interconnect lines and vias.

12. The method of claim 11 wherein said underfill layer comprises an organic polymer filled with silica beads.

13. The method of claim 11 including forming said barrier extending through said interconnection layer into contact with said semiconductor substrate.

14. The method of claim 13 wherein said underfill layer comprises an organic polymer filled with silica beads.

15. The method of claim 11 wherein said interconnection structure includes a low-k dielectric material.

16. The method of claim 15 wherein said low-k dielectric material comprises porous hydrogenated silicon oxycarbide (pSiCOH).

17. The method of claim 16 wherein said underfill layer comprises an organic polymer filled with silica beads.

18. The method of claim 15 wherein said underfill layer comprises an organic polymer filled with silica beads.

19. The method of claim 11 wherein said interconnection structure is recessed down to said substrate outboard from said trench.

20. The method of claim 19 wherein said trench has a bottom which is flared outwardly forming a trough wider than said trench at the bottom of said trench and wider than the width of said trench thereabove.

21. The method of claim 20 wherein said underfill layer comprises an organic polymer filled with silica beads.

22. The method of claim 19 wherein said underfill layer comprises an organic polymer filled with silica beads.