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Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

  • US 7,955,955 B2
  • Filed: 05/10/2007
  • Issued: 06/07/2011
  • Est. Priority Date: 05/10/2007
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor product comprising a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip with said semiconductor substrate having a top surface and a perimeter;

  • an active device (FEOL) layer on said top surface, a BEOL layer on top of said FEOL layer, and a barrier formed in said chip within said perimeter;

    comprisingthe step of cutting a trench extending down through said top surface of said semiconductor product, but extending only partially down into said substrate between said barrier and the outermost of said perimeter, prior to performing the following steps;

    forming a blanket underfill layer over said product completely covering said semiconductor product and completely filling said trench, anddicing said semiconductor product into chips.

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