Nanophotovoltaic devices

• US 7,955,965 B2
• Filed: 08/06/2010
• Issued: 06/07/2011
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Masimo Semiconductor Inc. (Masimo Corporation)
• Original Assignee: Spire Corporation
• Inventors: Moe, James G., Wojtczuk, Steven J., Little, Roger G.
• Primary Examiner(s): LE, THAO P
• Application Number:
  US12/851,893
• Publication Number:
  US 20100297803A1
• Time in Patent Office: 305 Days
• Field of Search: 257/103, 136/249, 438/597, 438/586
• US Class Current: 438/597
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: H01L 31/035281 Shape of the body
• CPC Class Codes: H01L 31/07 the potential barriers being only of the Schottky type
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5 microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier junction with the semiconductor core and the other forms an ohmic contact therewith. In other embodiment, the nanophotovoltaic device includes a semiconductor core comprising a p-n junction that is sandwiched between two metallic layers forming ohmic contacts with the core.

Claims

1. A method of forming nanophotovoltaic devices, comprising

providing a semiconductor-on-insulator wafer having a continuous buried insulating layer separating a thin upper layer from the bulk of the wafer,

forming a p-n junction in said upper wafer layer,

depositing a first metallic layer on an exposed surface of said thin upper layer so as to form an ohmic contact therewith,

removing the bulk portion of the wafer and said continuous insulating layer to generate a structure comprising said upper layer comprising a p-n junction and said metallic layer disposed on a surface thereof,

depositing a second metallic layer on an exposed surface of said thin layer opposed to said first metallic layer to form an ohmic contact therewith,

applying a photoresist to one of said metallic layers,

holographically patterning said resist to generate a two-dimensional holographic recording therein,

developing said patterned photoresist to generate a pattern of exposed and unexposed portions, and

etching away the exposed portions to generate a plurality of nanophotovoltaic devices.

2. The method of claim 1, wherein said upper layer is initially p-doped and said step of forming a p-n junction comprises:

implanting donor ions in a portion of said upper silicon layer to generate an n-doped portion adjacent to a p-doped portion.

3. The method of claim 1, further comprising selecting said semiconductor-on-insulator wafer to be a SIMOX wafer.

4. The method of claim 3, further comprising selecting said insulating layer to be a buried oxide layer.

5. The method of claim 1, wherein said step of holographically patterning the resist comprises

exposing the photoresist to a one-dimensional holographic line grating,

rotating the wafer by 90 degrees, and

exposing the photoresist to the line grating.

6. The method of claim 1, wherein said step of holographically patterning the resist comprises:

exposing the photoresist to a two-dimensional grating pattern.

7. The method of claim 1, wherein said holographic patterning provides a resolution of about 1000 nm.

8. The method of claim 1, wherein the step of etching away the exposed portions comprises employing a dry etching process.