Semiconductor element and display device using the same

• US 7,955,975 B2
• Filed: 07/21/2010
• Issued: 06/07/2011
• Est. Priority Date: 04/09/2002
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Murakami, Satoshi, Hayakawa, Masahiko, Yamazaki, Shunpei
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US12/840,349
• Publication Number:
  US 20100285661A1
• Time in Patent Office: 321 Days
• Field of Search: 438/668, 438/950, 257/E21.161, 257/E21.162
• US Class Current: 438/668
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/1341 Filling or closing of cells
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 2102/3026 : Top emission
• CPC Class Codes: H10K 2102/311 : Flexible OLED
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: Y10S 438/95 : Multilayer mask including nonradiation sensitive layer

Abstract

Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor, a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film, in which a first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first nitride insulating film covering a thin film transistor;

forming a photosensitive organic resin film over the first nitride insulating film;

forming a first opening portion exposing a part of the first nitride insulating film in the photosensitive organic resin film by exposure and development of the photosensitive organic resin film;

forming a second nitride insulating film covering a top surface of the photosensitive organic resin film and an inner wall surface of the first opening portion;

forming a second opening portion inside the first opening portion by etching the first nitride insulating film and the second nitride insulating film; and

forming an electrode electrically connected to an island-like semiconductor film in the thin film transistor through the second opening portion,

wherein a curvature radius of the inner wall surface of the photosensitive organic resin film continuously increases in a direction from a bottom portion of the first opening portion to a top portion of the first opening portion.

2. The method according to claim 1, wherein a contact angle (θ

) formed by the first nitride insulating film and the photosensitive organic resin film in a bottom end portion of the first opening portion satisfies 30°

<

θ

<

65°

.

3. The method according to claim 1, wherein a diameter of the first opening portion (φ

1) and a diameter of the second opening portion (φ

2) satisfy φ

1>

φ

2.

4. The method according to claim 1, wherein the second nitride insulating film is formed by sputtering method.

5. The method according to claim 1, wherein the second nitride insulating film is a silicon nitride film formed by a sputtering method using a high frequency discharge.

6. The method according to claim 1, wherein the photosensitive organic resin film is a positive type photosensitive organic resin film.

7. The method according to claim 1, wherein the photosensitive organic resin film is an acrylic film.

8. The method according to claim 1, wherein ultraviolet light is used for exposure.

9. The method according to claim 1, wherein the photosensitive organic resin film serves as a leveling film.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first nitride insulating film over a semiconductor film;

forming a photosensitive organic resin film over the first nitride insulating film;

exposing the photosensitive organic resin film;

wet etching the exposed photosensitive organic resin film so as to form an opening portion in the photosensitive organic resin film wherein a curvature radius of an inner wall surface of the photosensitive organic resin film continuously increases in a direction from a bottom portion of the opening portion to a top portion of the opening portion;

forming a second nitride insulating film over the photosensitive organic resin film and the opening portion of the photosensitive organic resin film;

dry etching the first nitride insulating film and the second nitride insulating film sequentially; and

forming a pixel electrode electrically connected to the semiconductor film though opening portions in the second nitride insulating film, the photosensitive organic resin film, and the first nitride insulating film.

11. The method according to claim 10, wherein the second nitride insulating film is formed by sputtering method.

12. The method according to claim 10, wherein the second nitride insulating film is a silicon nitride film formed by a sputtering method using a high frequency discharge.

13. The method according to claim 10, further comprising the step of heat treatment after the wet etching.

14. The method according to claim 10, wherein the photosensitive organic resin film is a positive type photosensitive organic resin film.

15. The method according to claim 10, wherein the photosensitive organic resin film is an acrylic film.

16. The method according to claim 10, wherein ultraviolet light is used for exposure.

17. The method according to claim 10, wherein the photosensitive organic resin film serves as a leveling film.

18. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first silicon nitride film over a semiconductor film;

forming a photosensitive organic resin film over the first silicon nitride film;

exposing the photosensitive organic resin film;

wet etching the exposed photosensitive organic resin film so as to form an opening portion in the photosensitive organic resin film wherein a curvature radius of an inner wall surface of the photosensitive organic resin film continuously increases in a direction from a bottom portion of the opening portion to a top portion of the opening portion;

forming a second silicon nitride film over the photosensitive organic resin film and the opening portion of the photosensitive organic resin film;

dry etching the first silicon nitride film and the second silicon nitride film sequentially; and

forming a pixel electrode electrically connected to the semiconductor film though opening portions in the second silicon nitride film, the photosensitive organic resin film, and the first silicon nitride film.

19. The method according to claim 18, further comprising the step of heat treatment after the wet etching.

20. The method according to claim 18, wherein the second silicon nitride film is formed by sputtering method.

21. The method according to claim 18, wherein the second silicon nitride film is formed by a sputtering method using a high frequency discharge.

22. The method according to claim 18, wherein the photosensitive organic resin film is a positive type photosensitive organic resin film.

23. The method according to claim 18, wherein the photosensitive organic resin film is an acrylic film.

24. The method according to claim 18, wherein ultraviolet light is used for exposure.

25. The method according to claim 18, wherein the photosensitive organic resin film serves as a leveling film.