Transistor and memory cell array

• US 7,956,387 B2
• Filed: 09/08/2006
• Issued: 06/07/2011
• Est. Priority Date: 09/08/2006
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schloesser, Till
• Primary Examiner(s): Bryant; Kiesha R
• Assistant Examiner(s): WRIGHT, TUCKER J
• Application Number:
  US11/517,558
• Publication Number:
  US 20080121961A1
• Time in Patent Office: 1,733 Days
• Field of Search: 257/302, 257/220, 257/242, 257/E27.06, 438/282, 438/272
• US Class Current: 257/220
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.

Claims

1. An integrated circuit comprising a transistor formed in a semiconductor substrate having a top surface, the transistor comprising:

first and second source/drain regions, the first and second source/drain regions having a first conductivity type;

a channel disposed between the first and second source/drain region, the channel having a second conductivity type, the second conductivity type being opposite to the first conductivity type;

a gate groove defined in the top surface of the semiconductor substrate and comprising an upper and a lower groove portion; and

a gate electrode for controlling an electrical current flowing in the channel in a first direction between the first and second source/drain regions, wherein the gate electrode is disposed in the lower groove portion of the gate groove and an uppermost surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate, the upper groove portion being filled with an insulating material, wherein, in a cross section perpendicular to the first direction and perpendicular to the top surface of the semiconductor substrate, the gate electrode encloses the channel at a top side and two lateral sides of the channel.

2. The integrated circuit of claim 1, wherein the gate electrode comprises a metal filling in the gate groove.

3. The integrated circuit of claim 1, wherein the first source/drain region is asymmetric with respect to the second source/drain region in a depth direction.

4. The integrated circuit of claim 1, wherein the first source/drain region comprises a different doping concentration than the second source/drain region.

5. The integrated circuit of claim 1, wherein the first source/drain region comprises a first doped portion having a higher doping concentration than a second doped portion forming part of the second source/drain region, the second doped portion being disposed at the same height as the first doped portion.

6. An integrated circuit comprising a transistor formed in a semiconductor substrate having a top surface, the transistor comprising:

first and second doped regions adjacent to the top surface;

a channel disposed between the first and second doped regions;

means for controlling an electrical current flowing in the channel in a first direction between the first and second doped regions, wherein the means for controlling the electrical current is disposed in a groove, the groove being defined in the top surface of the semiconductor substrate, wherein in a cross-section perpendicular to the first direction, the means for controlling the electric current encloses the channel at a top side and two lateral sides of the channel, and wherein a top surface of the means for controlling the electrical current is disposed beneath the top surface of the semiconductor substrate.

7. The integrated circuit of claim 6, wherein the first doped region is asymmetric with respect to the second doped region in a depth direction.

8. The integrated circuit of claim 6, wherein the first doped region comprises a different doping concentration than the second doped region.

9. The integrated circuit of claim 6, wherein the first doped region comprises a first doped portion having a higher doping concentration than a second doped portion forming part of the second doped region, the second doped portion being disposed at the same height as the first doped portion.

10. An integrated circuit comprising a transistor formed in a semiconductor substrate having a top surface, the transistor comprising:

first and a second source/drain regions;

a channel being disposed between the first and second source/drain regions;

a gate groove defined in the top surface of the semiconductor substrate and comprising an upper and a lower groove portion; and

a gate electrode for controlling an electrical current flowing in the channel in a first direction between the first and second source/drain regions, wherein the gate electrode is disposed in the lower groove portion of the gate groove and an uppermost surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate, the upper groove portion being filled with an insulating material, a boundary between the lower and the upper groove portion being disposed over its entire extent beneath the top surface, wherein, in a cross section perpendicular to the first direction and perpendicular to the top surface, the gate electrode encloses the channel at a top side and two lateral sides of the channel.

11. The integrated circuit of claim 10, wherein the gate electrode comprises a metal filling in the gate groove.

12. The integrated circuit of claim 10, wherein the first source/drain region is asymmetric with respect to the second source/drain region in a depth direction.

13. The integrated circuit of claim 10, wherein the first source/drain region comprises a different doping concentration than the second source/drain region.

14. The integrated circuit of claim 10, wherein the first source/drain region comprises a first doped portion having a higher doping concentration than a second doped portion forming part of the second source/drain region, the second doped portion being disposed at the same height as the first doped portion.