Method of forming a device wafer with recyclable support

• US 7,956,436 B2
• Filed: 08/27/2009
• Issued: 06/07/2011
• Est. Priority Date: 04/18/2007
• Status: Active Grant

• Current Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Original Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Inventors: Celler, George K.
• Primary Examiner(s): ANDUJAR, LEONARDO
• Application Number:
  US12/548,623
• Publication Number:
  US 20090315140A1
• Time in Patent Office: 649 Days
• Field of Search: 257/506, 257/E27.112, 438/464, 438/460
• US Class Current: 257/506
• CPC Class Codes: H01L 21/02032 by reclaiming or re-processing
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/67346 characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

Claims

1. A semiconductor construct comprising:

a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon;

a supporting substrate having upper and lower surfaces, with the upper surface of the supporting substrate having a plurality of holes extending therethrough;

a connecting bond present at an interface between the wafer and the substrate which is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface;

wherein the plurality of holes are configured to receive at least one loosening agent therethrough for weakening the connecting bond between the wafer and the substrate at the interface.

2. The construct of claim 1 wherein the wafer and supporting substrates have thicknesses to provide the construct thickness to be about 650 to 1000 microns, with constructs that have a diameter of 200 mm having a minimum thickness of approximately 725 μ

m, constructs that have a diameter of 300 mm having a minimum thickness of approximately 775 μ

m, and constructs that have a diameter of 450 mm having a minimum thickness of approximately 800 μ

m.

3. The construct of claim 1 which has a thickness which is substantially the same as the thickness of a standard wafer of the same diameter as the construct so that the construct can be processed in machines designed to hold standard wafers.

4. The construct of claim 1 wherein the holes that are formed have diameters between about 25 microns and about 100 microns.

5. The construct of claim 4 wherein the holes are separated from each other by a distance of between about 100 microns and about 1 mm.

6. The construct of claim 1, further comprising a coating of a thin layer of material on the supporting substrate and holes to prevent premature loosening or separation of the wafer and support substrate during device fabrication.

7. The construct of claim 1 wherein the wafer is a SOI wafer.

8. The construct of claim 1 which further comprises electronic devices on the first surface of the wafer.