Semiconductor package with patterning layer and method of making same

• US 7,956,453 B1
• Filed: 01/16/2008
• Issued: 06/07/2011
• Est. Priority Date: 01/16/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Do Hyeong, Kim, Bong Chan, Chung, Ji Young, Kim, Yoon Joo
• Primary Examiner(s): Fahmy; Wael M
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US12/015,428
• Time in Patent Office: 1,238 Days
• Field of Search: 257/738, 257/692, 257/693, 257/698, 257/784, 257/774, 257/E23.011, 257/E23.01, 257/773, 257/E23.079
• US Class Current: 257/692
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including one or more semiconductor dies which are electrically connected to an underlying substrate through the use of a conductive pattern which is at least partially embedded in a patterning layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate is at least one semiconductor die. The semiconductor die and the substrate are at least partially encapsulated by a patterning layer. Embedded in the patterning layer is a wiring pattern which electrically connects the semiconductor die to the conductive pattern. A portion of the wiring pattern is exposed in the patterning layer.

Claims

1. A semiconductor package, comprising:

a substrate including an insulative layer defining opposed first and second surfaces and having a first conductive pattern disposed on the first surface and a second conductive pattern disposed on the second surface and electrically connected to the first conductive pattern;

at least one semiconductor die mounted to the insulative layer and electrically connected to the first conductive pattern thereof;

a patterning layer defining a first surface, the patterning layer at least partially encapsulating the semiconductor die and at least partially covering the first conductive pattern and the first surface of the insulative layer, the second conductive pattern not being covered by the patterning layer; and

a wiring pattern embedded in the patterning layer and electrically connecting the semiconductor die to the first conductive pattern of the substrate, a portion of the wiring pattern being exposed in and substantially flush with the first surface of the patterning layer.

2. The semiconductor package of claim 1 further comprising a protective layer formed on the patterning layer and covering the portion of the wiring pattern exposed in the first surface thereof.

3. The semiconductor package of claim 1 wherein portions of the first and second conductive patterns are each covered by a solder mask.

4. The semiconductor package of claim 1 wherein the second conductive pattern includes a plurality of solder balls electrically connected thereto in a prescribed arrangement.

5. The semiconductor package of claim 1 wherein the wiring pattern comprises:

a first via pattern in electrical communication with the semiconductor die;

a second via pattern in electrical communication with the first conductive pattern; and

a connection pattern electrically connected to and extending between the first and second via patterns.

6. The semiconductor package of claim 5 wherein the connection pattern of the wiring pattern in exposed in and substantially flush with the first surface of the patterning layer.

7. A semiconductor package, comprising:

a substrate including an insulative layer defining opposed first and second surfaces and having a conductive pattern disposed on each of the first and second surfaces, the conductive patterns being electrically connected to each other in a prescribed manner;

a first patterning layer defining a first surface, the first patterning layer at least partially covering the first surface of the insulative layer and the conductive pattern disposed thereon, the conductive pattern disposed on the second surface of the insulative layer not being covered by the first patterning layer;

a first wiring pattern embedded in the first patterning layer and electrically connected to the conductive pattern disposed on the first surface of the insulating layer, a portion of the first wiring pattern being exposed in and substantially flush with the first surface of the first patterning layer; and

a first semiconductor die electrically connected to the first wiring pattern.

8. The semiconductor package of claim 7 wherein the first semiconductor die is at least partially encapsulated by the first patterning layer and electrically connected to the conductive pattern disposed on the first surface of the insulative layer by the first wiring pattern.

9. The semiconductor package of claim 8, further comprising:

a second semiconductor die electrically connected to the conductive pattern disposed on the first surface of the insulative layer;

a second patterning layer defining a first surface, the second patterning layer at least partially encapsulating the second semiconductor die and the first patterning layer; and

a second wiring pattern embedded in the second patterning layer and electrically connecting the second semiconductor die to the conductive pattern disposed on the first surface of the insulative layer, a portion of the second wiring pattern being exposed in and substantially flush with the first surface of the second patterning layer.

10. The semiconductor package of claim 9 further comprising a protective layer formed on the first surface of the second patterning layer and covering the portion of the second wiring pattern exposed therein.

11. The semiconductor package of claim 10 wherein the second patterning layer is sized and configured to cover the portion of the first wiring pattern exposed in the first surface of the first patterning layer.

12. The semiconductor package of claim 9 wherein the substrate further comprises:

a first conductive pattern disposed on the first surface;

a second conductive pattern disposed on the first surface;

a third conductive pattern disposed on the second surface and electrically connected to the first conductive pattern; and

a fourth conductive pattern disposed on the second surface and electrically connected to the second conductive pattern;

the first semiconductor die being electrically connected to the first conductive pattern, with the second semiconductor die being electrically connected to the second conductive pattern and the first patterning layer covering the first semiconductor die and at least portions of the first conductive pattern, the second conductive pattern and the first surface of the insulative layer, and not covering the third and fourth conductive patterns.

13. The semiconductor package of claim 12 wherein the third and fourth conductive patterns each include a plurality of solder balls electrically connected thereto in a prescribed arrangement.

14. The semiconductor package of claim 12 wherein the first wiring pattern comprises:

a first via pattern in electrical communication with the first semiconductor die;

a second via pattern in electrical communication with the first conductive pattern; and

a connection pattern electrically connected to and extending between the first and second via patterns.

15. The semiconductor package of claim 14 wherein the connection pattern of the first wiring pattern in exposed in and substantially flush with the first surface of the first patterning layer.

16. The semiconductor package of claim 14 wherein the second wiring pattern comprises:

a first via pattern in electrical communication with the second semiconductor die;

a second via pattern in electrical communication with the second conductive pattern; and

a connection pattern electrically connected to and extending between the first and second via patterns.

17. The semiconductor package of claim 16 wherein the connection pattern of the second wiring pattern is exposed in and substantially flush with the first surface of the second patterning layer.

18. The semiconductor package of claim 7, further comprising:

a second patterning layer defining a first surface, the second patterning layer at least partially encapsulating the first semiconductor die and the first patterning layer;

a second wiring pattern embedded in the second patterning layer and electrically connected to the first semiconductor die, a portion of the second wiring pattern being exposed in and substantially flush with the first surface of the second patterning layer;

a second semiconductor die electrically connected to the second wiring pattern; and

a third patterning layer defining a first surface, the third patterning layer at least partially encapsulating the second semiconductor die and the second patterning layer.

19. The semiconductor package of claim 18, further comprising:

a third wiring pattern embedded in the third patterning layer and electrically connected to the second semiconductor die, a portion of the third wiring pattern being exposed in and substantially flush with the first surface of the third patterning layer;

a third semiconductor die electrically connected to the third wiring pattern; and

a fourth patterning layer at least partially encapsulating the third semiconductor die and the third patterning layer.