Thin film structures with negative inductance and methods for fabricating inductors comprising the same

• US 7,956,715 B2
• Filed: 04/21/2009
• Issued: 06/07/2011
• Est. Priority Date: 04/21/2008
• Status: Active Grant

• Current Assignee: University of Dayton
• Original Assignee: University of Dayton
• Inventors: Sarangan, Andrew, Widjaja, Agus
• Primary Examiner(s): Enad; Elvin G
• Assistant Examiner(s): CHAN, TSZFUNG JACKIE
• Application Number:
  US12/427,296
• Publication Number:
  US 20090261936A1
• Time in Patent Office: 777 Days
• Field of Search: 336/83, 336/200, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10

Abstract

An inductor structure comprising a substrate and a planar conductor structure on a surface of the substrate, and methods for fabricating an inductor structure. The planar conductor structure may comprise a vertical stack of three or more multilayer films. Each multilayer film may comprise a first layer of a first metal, defining a first vertical thickness, and a second layer of a second metal, defining a second vertical thickness. The metals and thicknesses are chosen such that the inductor exhibits a negative electrical self-inductance when an electrical signal is transmitted from a first contact point to a second contact point.

Claims

1. An inductor comprising a substrate and a planar conductor structure on a surface of the substrate, the planar conductor structure having a total thickness of from 0.1 μ

m to 5 μ

m and comprising

a vertical stack of at least fourteen multilayer films, each multilayer film comprising

a first layer consisting essentially of aluminum, the first layer defining a first vertical thickness; and

a second layer consisting essentially of copper, the second layer covering the first layer and defining a second vertical thickness,

such that the first vertical thickness is substantially the same in all multilayer films of the vertical stack and such that the ratio of the first vertical thickness to the second vertical thickness is about 2 in all multilayer films of the vertical stack, the vertical stack being formed by a repetitive series of alternating depositions of first layers of aluminum and second layers of copper onto the substrate;

a first contact point; and

a second contact point,

the inductor exhibiting a negative electrical self-inductance when an electric signal of alternating current having a frequency of up to 10 MHz is transmitted from the first contact point to the second contact point.

2. The inductor of claim 1, wherein the planar conductor structure is a series of successive spirals defining a number of turns, a track width, a spacing, an inner radius, and a shape, the shape being selected from the group consisting of a triangle, a square, a rectangle, a higher-order polygon, an ellipse, and a circle.

3. The inductor of claim 2, wherein the number of turns is 1 to 20, the track width is 0.1 μ

m to 200 μ

m, the spacing is 0.1 μ

m to 200 μ

m, and the inner radius is 0.2 μ

m to 400 μ

m.

4. The inductor of claim 3, wherein the planar conductor structure comprises at least thirty multilayer films.

5. A microelectronic device comprising at least one negative inductor and at least one positive inductor having a positive parasitic inductance and wired in series with the at least one negative inductor, the at least one negative inductor compensating the positive parasitic inductance of the at least one positive inductor, the at least one negative inductor being an inductor according to claim 1.