Systems and methods for synchronous, retimed analog to digital conversion
First Claim
1. A retimed analog to digital converter circuit, the circuit comprising:
- a first set of sub-level interleaves, wherein the first set of sub-level interleaves includes;
a first sub-level interleave, wherein the first sub-level interleave includes a first set of comparators synchronized to a first clock phase;
a second sub-level interleave, wherein the second sub-level interleave includes a second set of comparators synchronized to a second clock phase;
a second set of sub-level interleaves, wherein the second set of sub-level interleaves includes;
a third sub-level interleave, wherein the third sub-level interleave includes a third set of comparators synchronized to a third clock phase;
a fourth sub-level interleave, wherein the fourth sub-level interleave includes a fourth set of comparators synchronized to a fourth clock phase; and
a global interleave, wherein the global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and wherein the global interleave selects one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves.
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Abstract
Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
75 Citations
20 Claims
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1. A retimed analog to digital converter circuit, the circuit comprising:
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a first set of sub-level interleaves, wherein the first set of sub-level interleaves includes; a first sub-level interleave, wherein the first sub-level interleave includes a first set of comparators synchronized to a first clock phase; a second sub-level interleave, wherein the second sub-level interleave includes a second set of comparators synchronized to a second clock phase; a second set of sub-level interleaves, wherein the second set of sub-level interleaves includes; a third sub-level interleave, wherein the third sub-level interleave includes a third set of comparators synchronized to a third clock phase; a fourth sub-level interleave, wherein the fourth sub-level interleave includes a fourth set of comparators synchronized to a fourth clock phase; and a global interleave, wherein the global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and wherein the global interleave selects one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for analog to digital conversion, the method comprising:
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performing a first set of analog to digital conversions using a first set of comparators; performing a second set of analog to digital conversions using a second set of comparators; performing a third set of analog to digital conversions using a third set of comparators; performing a fourth set of analog to digital conversions using a fourth set of comparators; selecting a result from the first set of analog to digital conversions based at least in part on a first registered result to provide a first selected result; selecting a result from the second set of analog to digital conversions based at least in part on the first selected result to provide a second selected result; selecting a result from the third set of analog to digital conversions based at least in part on the second registered result to provide a third selected result; and selecting a result from the fourth set of analog to digital conversions based at least in part on the third selected result to provide a fourth selected result; registering the fourth selected result to provide the first registered result; and registering the second selected result to provide the second registered result. - View Dependent Claims (13, 14)
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15. A communication system, the system comprising:
a receiver including a retimed analog to digital converter, wherein the retimed analog to digital converter includes; a first set of sub-level interleaves, wherein the first set of sub-level interleaves includes; a first sub-level interleave, wherein the first sub-level interleave includes a first set of comparators synchronized to a first clock phase; a second sub-level interleave, wherein the second sub-level interleave includes a second set of comparators synchronized to a second clock phase; a second set of sub-level interleaves, wherein the second set of sub-level interleaves includes; a third sub-level interleave, wherein the first sub-level interleave includes a third set of comparators synchronized to a third clock phase; a fourth sub-level interleave, wherein the fourth sub-level interleave includes a fourth set of comparators synchronized to a fourth clock phase; and a global interleave, wherein the global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and wherein the global interleave selects one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. - View Dependent Claims (16, 17, 18, 19, 20)
Specification