Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same

• US 7,957,206 B2
• Filed: 04/04/2008
• Issued: 06/07/2011
• Est. Priority Date: 04/04/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bauser, Philippe
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US12/080,642
• Publication Number:
  US 20090251958A1
• Time in Patent Office: 1,159 Days
• Field of Search: 365/174, 365/189.15, 365/189.07, 365/189.09, 365/203, 365/204, 365/233.17, 365/242
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation.

Claims

1. An integrated circuit device comprising:

a memory cell array including;

a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor;

a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line;

memory cell control circuitry, coupled to the memory cell array, to generate one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, the electrically floating body transistor associated with a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line;

sense amplifier circuitry having an input which is electrically coupled to the bit line to receive a signal which is responsive to the current conducted on the bit line by the electrically floating body transistor of the selected memory cell and, in response thereto, to (i) sense the data state stored in the selected memory cell and (ii) output a signal which is representative thereof;

current regulation circuitry, electrically coupled to the bit line, to sink or source at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation; and

sensing circuitry, coupled between the bit line and the current regulation circuitry, to responsively couple the current regulation circuitry to the bit line during only the portion of the read operation.

2. The integrated circuit device of claim 1 wherein the sensing circuitry includes a transistor, wherein the transistor provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.

3. The integrated circuit device of claim 2 wherein the transistor is a p-channel or n-channel type transistor.

4. The integrated circuit device of claim 1 wherein the sensing circuitry includes a switch which provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.

5. The integrated circuit device of claim 1 wherein the sense amplifier circuitry senses the data state of the selected memory cell using an amplitude of the voltage on the bit line.

6. The integrated circuit device of claim 5 wherein the amplitude of the voltage on the bit line is responsive to the amount of current on the bit line conducted by the electrically floating body transistor associated with the selected memory cell during the read operation.

7. The integrated circuit device of claim 1 wherein the current regulation circuitry includes a current mirror circuit.

8. The integrated circuit device of claim 1 wherein the portion of the read operation includes the end of the read operation.

9. The integrated circuit device of claim 1 wherein the electrically floating body transistor associated with the selected memory cell conducts a channel current which is representative of the data state of the memory cell on the bit line.

10. The integrated circuit device of claim 1 wherein the electrically floating body transistor associated with the selected memory cell conducts a bipolar transistor current which is representative of the data state of the memory cell on the bit line.

11. An integrated circuit device comprising:

a memory cell array including;

a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell is programmable to store one of a plurality of data states;

a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line;

memory cell control circuitry, coupled to the memory cell array, to generate one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line;

sense amplifier circuitry having an input which is electrically coupled to the bit line to receive a signal which is responsive to the current conducted on the bit line, and, in response thereto, to (i) sense the data state stored in the selected memory cell and (ii) output a signal which is representative thereof;

current regulation circuitry, electrically coupled to the bit line, to sink or source at least a portion of the current conducted on the bit line by the selected memory cell during only a portion of the read operation; and

sensing circuitry, coupled between the bit line and the current regulation circuitry, to responsively couple the current regulation circuitry to the bit line during only the portion of the read operation.

12. The integrated circuit device of claim 11 wherein the sensing circuitry includes a transistor, wherein the transistor provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.

13. The integrated circuit device of claim 12 wherein the transistor is a p-channel or n-channel type transistor.

14. The integrated circuit device of claim 11 wherein the sensing circuitry includes a switch which provides a current path between the bit line and the current regulation circuitry in response to a predetermined voltage on the bit line.

15. The integrated circuit device of claim 11 wherein the sense amplifier circuitry senses the data state of the selected memory cell using an amplitude of the voltage on the bit line.

16. The integrated circuit device of claim 15 wherein the amplitude of the voltage on the bit line is responsive to the amount of current on the bit line conducted by an electrically floating body transistor associated with the selected memory cell during the read operation.

17. The integrated circuit device of claim 11 wherein the current regulation circuitry includes a current mirror circuit.

18. The integrated circuit device of claim 11 wherein the portion of the read operation includes the end of the read operation.

19. An integrated circuit device comprising:

a memory cell array including;

a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor;

a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line;

means for generating one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, the electrically floating body transistor associated with a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line;

means for receiving a signal which is responsive to the current conducted on the bit line by the electrically floating body transistor of the selected memory cell and, in response thereto, for (i) sensing the data state stored in the selected memory cell and (ii) outputting a signal which is representative thereof;

current regulation means for sinking or sourcing at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation; and

means for responsively and electrically coupling the current regulation means to the bit line during only the portion of the read operation.

20. A method of reading a memory cell which is disposed on integrated circuit device comprising a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, wherein the memory cell array includes a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor, the method comprising:

generating read control signals to perform a read operation wherein, in response to read control signals, the electrically floating body transistor associated of a selected memory cell conducts a current which is representative of the data state of the memory cell on a bit line;

determining the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the electrically floating body transistor and, in response thereto, outputting a data state signal which is representative of the data state of the memory cell on the bit line;

sinking or sourcing at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation; and

sensing a predetermined voltage on the bit line, wherein sinking or sourcing at least a portion of the current conducted on the bit line further includes sinking or sourcing a substantial portion of the current conducted on the bit line by the electrically floating body transistor after sensing the predetermined voltage on the bit line.

21. The method of claim 20 wherein portion of the read operation includes the end of the read operation.

22. The method of claim 20 further including providing a current path during only a portion of the read operation to sink or source at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell.

23. The method of claim 20 wherein determining the data state stored in the selected memory cell using the signal which is responsive to the current conducted by the electrically floating body transistor further includes using an amplitude of the voltage on the bit line to determine the data state stored in the selected memory cell.

24. The method of claim 20 wherein the amplitude of the voltage on the bit line is responsive to the amount of current conducted on the bit line during the read operation.