Fast phase-frequency detector arrangement

• US 7,957,500 B2
• Filed: 04/13/2010
• Issued: 06/07/2011
• Est. Priority Date: 03/29/2004
• Status: Expired due to Fees

• Current Assignee: III Holdings 6, LLC (Intellectual Ventures LLC)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Sanduleanu, Mihai Adrian Tiberiu, Stikvoort, Eduard Ferdinand
• Primary Examiner(s): Corrielus; Jean B
• Application Number:
  US12/759,519
• Publication Number:
  US 20100205488A1
• Time in Patent Office: 420 Days
• Field of Search: 375/355, 375374-376, 327/156, 327/157, 327/159
• US Class Current: 375/374
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence

Abstract

A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L1, L2) for sampling a quadrature component (CKQ) of the reference signal based on the input signal, to generate a first binary signal (PDQ); second latch circuitry (L3, L4) for sampling an in-phase component (CKI) of the reference signal based on the input signal, to-generate a second binary signal (PD I); third latch circuitry (L5) for sampling the first binary signal based on the second binary signal, to generate the frequency error signal (FD). The detector further comprising control circuitry (TS) for selectively suppressing operation of a charge pump (82) to which the first binary signal (PDQ) is supplied, in response to a control signal derived from the second binary signal.

Claims

1. A detector arrangement for detecting a frequency error between an input signal and a reference signal, said detector arrangement comprising:

a first latch for sampling a quadrature component of said reference signal based on said input signal, to generate a first binary signal;

a second latch for sampling an in-phase component of said reference signal based on said input signal, to generate a second binary signal;

a third latch for sampling said first binary signal based on said second binary signal, to generate the frequency error signal; and

a controller, to which said frequency error signal is supplied, for selectively suppressing operation of a charge pump circuit in response to a control signal derived from said second binary signal.

2. A detector arrangement according to claim 1, wherein said first and second latches each comprise a double-edge triggered flip-flop arrangement.

3. A detector arrangement according to claim 2, wherein each double-edge triggered flip-flop arrangement comprises first and second D-latch circuits receiving said input signal and being respectively controlled by a direct version and an inversed version of the respective component of said reference signal, and a multiplexer circuit being controlled by said direct version and said inversed version of said respective component of said reference signal, wherein outputs of said first and second D-latch circuits are coupled to inputs of said multiplexer circuit.

4. A detector arrangement according to claim 1, wherein said third latch comprises a D-latch circuit receiving said first binary signal and being controlled by said second binary signal.

5. A detector arrangement according to claim 1, wherein said reference signal is a clock signal to be recovered from said input signal.

6. A detector arrangement according to claim 1, wherein said first and second binary signals are supplied to said third latch via at least one of respective amplifier and level shifter circuits.

7. A detector arrangement according to claim 6, wherein said amplifier circuits each comprise a combination of a feedback amplifier and a feedforward amplifier.

8. A recovery circuit for recovering timing information for random data, said recovery circuit comprising a detector arrangement according to claim 1, wherein said frequency error signal generated by said detector arrangement is supplied to said controller, and wherein a frequency-locked state is signaled by said control signal derived from said second binary signal generated by said detector arrangement.

9. A method of detecting a frequency error between an input signal and a reference signal, said method comprising the steps of:

sampling a quadrature component of said reference signal based on said input signal, to generate a first binary signal using a first latch of a detector arrangement;

sampling an in-phase component of said reference signal based on said input signal, to generate a second binary signal using a second latch of the detector arrangement;

sampling said first binary signal based on said second binary signal, to generate the frequency error signal using a third latch of the detector arrangement; and

selectively suppressing operation of a charge pump circuit in response to a control signal derived from said second binary signal.

10. A detector arrangement for detecting a frequency error between an input signal and a reference signal, said detector arrangement comprising:

a first latch for sampling a quadrature component of said reference signal based on said input signal, to generate a first binary signal;

a second latch for sampling an in-phase component of said reference signal based on said input signal, to generate a second binary signal;

a third latch for sampling said first binary signal based on said second binary signal, to generate the frequency error signal; and

a controller for selectively suppressing operation of a charge pump circuit to which said first binary signal is supplied, in response to a control signal derived from said second binary signal;

wherein said first and second latches each comprise a double-edge triggered flip-flop arrangement.

11. A detector arrangement according to claim 10, wherein said double-edge triggered flip-flop arrangement comprises first and second D-latch circuits receiving said input signal and being respectively controlled by a direct version and an inversed version of the respective component of said reference signal, and a multiplexer circuit being controlled by said direct version and said inversed version of said respective component of said reference signal, wherein outputs of said first and second D-latch circuits are coupled to inputs of said multiplexer circuit.