Support of deep power savings mode and partial good in a thermal management system

• US 7,957,848 B2
• Filed: 11/04/2008
• Issued: 06/07/2011
• Est. Priority Date: 11/29/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Johns, Charles Ray, Wang, Michael Fan
• Primary Examiner(s): Masinick; Michael D
• Application Number:
  US12/264,660
• Publication Number:
  US 20090048720A1
• Time in Patent Office: 945 Days
• Field of Search: 700/299, 713/300, 713/320
• US Class Current: 700/299
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/015 using microstructures, e.g. made of silicon
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor is monitored in response to at least one of the plurality of digital thermal sensors being functional. A functional digital thermal sensor is disabled in response to the at least one unit being in a power savings mode.

Claims

1. A computer implemented method for managing a thermal management system in an integrated circuit, comprising:

determining if a plurality of digital thermal sensors is indicated as faulty or functional;

responsive to at least one of the plurality of digital thermal sensors being functional, monitoring a power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor; and

responsive to the at least one unit being in a power savings mode, disabling the functional digital thermal sensor by masking off the functional digital thermal sensor, wherein masking off the functional digital thermal sensor comprises resetting a current temperature status register associated with the functional digital thermal sensor, stopping communications between the status register and the functional digital thermal sensor, and generating a signal to indicate the functional digital thermal sensor is currently masked and should not participate in thermal management tasks.

2. The method of claim 1, wherein the determining, monitoring, and disabling steps are performed by a thermal management control state machine residing within the integrated circuit.

3. The method of claim 1, further comprising:

responsive to at least one of the plurality of digital thermal sensors being functional, determining if the at least one unit associated with the functional digital thermal sensor is faulty; and

responsive to the at least one unit associated with the functional digital thermal sensor being faulty, disabling the functional digital thermal sensor.

4. The method of claim 1, further comprising:

monitoring the power savings mode of the at least one unit; and

responsive to the at least one unit exiting from the power savings mode, enabling the functional digital thermal sensor.

5. The method of claim 4, wherein enabling the functional digital thermal sensor further comprises:

resuming communications between a current temperature status register and the functional digital thermal sensor;

resetting the status register associated with the functional digital thermal sensor to a current temperature; and

generating a signal to indicate the functional digital thermal sensor should participate in thermal management tasks.

6. The method of claim 1, further comprising:

responsive to the at least one of the plurality of digital thermal sensors being faulty, masking off the faulty digital thermal sensor.

7. The method of claim 6, wherein masking off the faulty digital thermal sensor comprises:

resetting a current temperature status register associated with the faulty digital thermal sensor;

stopping communications between the status register and the faulty digital thermal sensor; and

generating a signal to indicate the faulty digital thermal sensor is currently masked and should not participate in thermal management tasks.

8. The method of claim 1, wherein the integrated circuit is a heterogeneous multi-core processor.

9. The method of claim 8, wherein the functional digital thermal sensor resides within one of the cores of the heterogeneous multi-core processor.

10. The method of claim 8, wherein the functional digital thermal sensor resides within the heterogeneous multi-core processor, but not within a core.

11. A data processing system comprising:

a bus;

a memory coupled to the bus, wherein the memory includes a set of instructions; and

a integrated circuit coupled to the bus, wherein the integrated circuit executes the set of instructions to determine if a plurality of digital thermal sensors is indicated as faulty or functional;

monitor a power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor in response to at least one of the plurality of digital thermal sensors being functional; and

disable the functional digital thermal sensor responsive to the at least one unit being in a power savings mode by masking off the functional digital thermal sensor, wherein masking off the functional digital thermal sensor comprises resetting a current temperature status register associated with the functional digital thermal sensor, stopping communications between the status register and the functional digital thermal sensor, and generating a signal to indicate the functional digital thermal sensor is currently masked and should not participate in thermal management tasks.

12. The system of claim 11, wherein the integrated circuit executes the set of instructions to determine if the at least one unit associated with the functional digital thermal sensor is faulty in response to at least one of the plurality of digital thermal sensors being functional;

and disable the functional digital thermal sensor in response to the at least one unit associated with the functional digital thermal sensor being faulty.

13. The system of claim 11, wherein the integrated circuit executes the set of instructions to monitor the power savings mode of the at least one unit;

and enable the functional digital thermal sensor in response to the at least one unit exiting from the power savings mode.

14. The system of claim 11, wherein the integrated circuit executes the set of instructions to mask off the faulty digital thermal sensor in response to the at least one of the plurality of digital thermal sensors being faulty.

15. A processor, comprising:

at least one processing core;

a thermal management control state machine; and

a digital thermal sensor, wherein the processor executes a set of instructions to determine, using the state machine, if a plurality of digital thermal sensors is indicated as faulty or functional;

monitor, using the state machine, a power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor responsive to at least one of the plurality of digital thermal sensors being functional; and

disable, using the state machine, the functional digital thermal sensor in response to the at least one unit being in a power savings mode by masking off the functional digital thermal sensor, wherein masking off the functional digital thermal sensor comprises resetting a current temperature status register associated with the functional digital thermal sensor, stopping communications between the status register and the functional digital thermal sensor, and generating a signal to indicate the functional digital thermal sensor is currently masked and should not participate in thermal management tasks.

16. The processor of claim 15, wherein the processor executes the set of instructions to determine, using the state machine, if the at least one unit associated with the functional digital thermal sensor is faulty in response to at least one of the plurality of digital thermal sensors being functional;

and disable, using the state machine, the functional digital thermal sensor in response to the at least one unit associated with the functional digital thermal sensor being faulty.

17. The processor of claim 15, wherein the processor executes the set of instructions to monitor, using the state machine, the power savings mode of the at least one unit;

and enable, using the state machine, the functional digital thermal sensor in response to the at least one unit exiting from the power savings mode.

18. The processor of claim 15, wherein the processor executes the set of instructions to mask off, using the state machine, the faulty digital thermal sensor in response to the at least one of the plurality of digital thermal sensors being faulty.