System and method for capacity planning for systems with multithreaded multicore multiprocessor resources

• US 7,957,948 B2
• Filed: 08/22/2007
• Issued: 06/07/2011
• Est. Priority Date: 08/22/2007
• Status: Active Grant

• Current Assignee: HyPerformix, Inc. (Broadcom, Inc.)
• Original Assignee: HyPerformix, Inc. (Broadcom, Inc.)
• Inventors: Zink, Kenneth C., Walton, Christopher B., Neuse, Douglas M.
• Primary Examiner(s): Shah; Kamini S
• Assistant Examiner(s): PATEL, SHAMBHAVI K
• Application Number:
  US11/895,176
• Publication Number:
  US 20090055823A1
• Time in Patent Office: 1,385 Days
• Field of Search: 703/13, 703/2, 703/22, 703/32, 702/176, 702/179, 702/186, 702/187, 702/188, 710/18, 717/103
• US Class Current: 703/13
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 11/3442 for planning or managing the needed capacity
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.

Claims

1. A method of calculating a system scalability factor of a computer processor system including a processor, the processor having a core, the core capable of running a thread, the thread capable of supporting a task and the processor running an operating system;

the method comprising;

estimating an initial value of an operating system scalability factor;

estimating a thread scalability factor;

estimating a CPU scalability factor;

estimating a processor core scalability factor;

iteratively combining the initial value of the operating system scalability factor, the thread scalability factor, the CPU scalability factor and the processor core scalability factor in an equation having a set of linear elements and a set of exponential elements to arrive at a result;

the step of iteratively combining further comprising the steps of;

a. grouping a set of measured performance records into a dataset;

b. computing a set of scalable processing quantities for the dataset;

the step of computing further comprising the steps of;

i. counting a number of active threads servicing CPU requests as a first number of active elements, N[1];

ii. counting a number of CPUs having active threads as a second number of active elements, N[2];

iii. counting a number of cores per CPU having active threads as a third number of active elements, N[3]; and

,

iv. counting a number of active threads per core as a fourth number of active elements, N[4];

c. normalizing the set of scalable processing quantities by a corresponding number of active elements to produce a set of normalized scalabilities; and

d. determining the result as a product of the normalized scalabilities;

combining the result with a measured performance parameter to arrive at an error;

comparing the error to a predetermined maximum error;

repeating the step of iteratively combining if the error is greater than the predetermined maximum error;

accepting the result as the system scalability factor of the computer processor system.

2. The method of claim 1 including the additional step of setting the operating system scalability factor, the thread scalability factor, the CPU scalability factor and the processor core scalability factor to a value of one as a default estimate.

3. The method of claim 1 wherein the step of computing a set of scalable processing quantities further comprises the additional steps of:

associating a first linear scalability factor L[1] and a first exponential scalability factor a[1] to the operating system scalability factor;

associating a second linear scalability factor L[2] and a second exponential scalability factor a[2] to the CPU scalability factor;

associating a third linear scalability factor L[3] and a third exponential scalability factor a[3] to the processor core scalability factor;

associating a fourth linear scalability factor L[4] and a first exponential scalability factor a[4] to the thread scalability factor;

computing the set of scalable processing quantities SP[i] for i in the range 1 to 4 according to the equation;

SP[i]=(1+L[i]×

(N[i]−

1))×

a[i]<sup>(N[i]−

1)</sup>.

4. The method of claim 3 wherein the step of normalizing the set of scalable processing quantities by a corresponding number of active elements to produce a set of normalized scalabilities comprises the additional step of:

computing the normalized scalabilities S[i] for i in the range 1 to 4 according to the equation;

S[i]=SP[i]/N[i].

5. The method of claim 4 wherein determining the result as a product of the normalized scalabilities is calculated as a system scalability, SS[i], for i in the range 1 to 4 according to the equation:

SS[i]=Π

s[i].

6. The method of claim 1 wherein the step of computing a set of scalable processing quantities comprises the additional steps of:

associating a total number of active threads to a first number of active elements, N[1];

counting a number of CPUs having active threads as a second number of active elements, N[2];

counting a number of cores per CPU having active threads as a third number of active elements, N[3];

counting a number of active threads per core as a fourth number of active elements, N[4];

setting the total number of active threads equal to;

N[1]=N[2]×

N[3]×

N[4].

7. The method of claim 6 including the additional step of computing an equivalent CPU scalability factor, EquivCPU, from the result of an estimated system scalability, ESS,

as:

EquivCPU=ESS/N[1].

8. The method of claim 7 wherein the step of combining the result with a measured performance parameter to arrive at an error includes the additional steps of:

calculating a throughput rate, R_calc, from a measured single thread performance, S_meas taken from the set of measured performance records, according to the formula;

R_calc=S_meas×

EquivCPU;

computing the error using R_calc and a set of measured throughput rates R_meas from the set of measured performance records, according to the formula;

9. The method of claim 8 including the further step of deriving the measured single thread performance from SPECint data gathered from a web site.

10. The method of claim 8 including the further step of deriving the measured throughput rate from SPECint_rate data gathered from a web site.

11. The method of claim 1 wherein the step of iteratively combining the initial value of the operating system scalability factor, the thread scalability factor, the CPU scalability factor and the processor core scalability factor includes the additional step of adjusting the set of linear elements and the set of exponential elements.

12. The method of claim 3 including the iterative steps subsequent to the step of computing a set of scalable processing quantities of:

adjusting at least one of the group of L[1], L[2], L[3], L[4], a[1], a[2], a[3] and a[4];

recomputing the set of scalable processing quantities SP[i].