Supplemental communication interface

• US 7,958,291 B2
• Filed: 10/10/2006
• Issued: 06/07/2011
• Est. Priority Date: 10/10/2006
• Status: Expired due to Fees

• Current Assignee: Atmel Rousset S.A.S. (Microchip Technology Incorporated)
• Original Assignee: Atmel Rousset S.A.S. (Microchip Technology Incorporated)
• Inventors: Parlange, Dominique, Renahy, Florent
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US11/548,104
• Publication Number:
  US 20080147923A1
• Time in Patent Office: 1,701 Days
• Field of Search: 710/8, 710/11, 710/14, 710/71, 710/72, 710/100, 710/107, 710/110, 710/22, 710/305, 370/395, 370/438, 370/522, 375/242, 375/269, 375/356, 712/38, 713/322, 713/600
• US Class Current: 710/71
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

An apparatus includes a first interface having a communication channel through which data is transmitted to or received from a target device and a first control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel. The apparatus also includes a second interface having a second control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel. A circuit in the apparatus harmonizes the contents of the first control register and the second control register, such that an external controller can control transmission or reception of data through the communication channel by providing control data in a first format to the first control register or by providing alternate control data in a second different format to the second control register.

Claims

1. An apparatus comprising:

a first interface coupled to a first device and having;

a communication channel through which data is transmitted to or received from a target device that is coupled to the first interface by the communication channel;

a first transmit status register that specifies, in a first format, a transmit buffer status for the first interface; and

a first control register that controls, based at least in part on its contents, transmission of data by the first interface and through the communication channel, the contents of the first control register being in the first format and including data specifying the transmit buffer status for the first interface;

a second interface coupled to the first interface and the first device, the second interface having;

a second transmit status register that specifies, in a second different format, the transmit buffer status for the first interface; and

a second control register that controls, based at least in part on its contents, transmission of data by the first interface and through the communication channel, contents of the second control register that are used to control transmission being in the second different format and including data specifying the transmit buffer status for the first interface; and

a circuit, coupled to the first interface and the second interface, that translates contents of the first control register from the first format to the second different format and translates contents of the second control register from the second different format to the first format, such that a same transmit buffer status is specified by both of the first control register and the second control register, wherein transmission of data is initiated by the first interface in response to the first control register receiving first control data in the first format from the first device, and wherein transmission of data is initiated by the first interface in response to the second control register receiving the first control data in the second different format from the first device.

2. The apparatus of claim 1, wherein the communication channel comprises a physical serial communication link, and wherein the first control register and the second control register each control transmission or reception of data using a shift register.

3. The apparatus of claim 2, wherein the physical serial communication link implements serial communication between two or more devices, the serial communication substantially adhering to a serial peripheral interface (SPI) protocol, an inter-integrated circuit (I²C) protocol, a 1-wire bus protocol, a system management bus (SMBus) protocol, or a proprietary serial communication protocol.

4. The apparatus of claim 1, wherein the second interface comprises a pointer that identifies a portion of the transmit buffer.

5. The apparatus of claim 4, wherein the second interface comprises a buffer control circuit that alters the pointer in response to subsequent, different contents of the second control register.

6. The apparatus of claim 1, wherein the transmit buffer includes a plurality of portions, each portion corresponding to a discrete quantum of data that can be processed by the communication channel at one time.

7. The apparatus of claim 6, wherein the quantum of data is one byte.

8. The apparatus of claim 6, wherein each portion of the plurality of portions is memory-mapped to a discrete address value and individually addressable through the discrete address value by the first device.

9. The apparatus of claim 1, wherein the first interface is a discrete, physical integrated circuit that is included in the apparatus.

10. The apparatus of claim 1, wherein the first interface is a preconfigured portion of an integrated circuit or a programmable device selected from the group consisting of programmable logic devices (PLDs) and field programmable gate arrays (FPGAs).

11. The apparatus of claim 1, wherein each of the first and second interface comprises additional registers, wherein the second interface comprises fewer total registers than the first interface.

12. The apparatus of claim 1, wherein the second interface is configured to automate more functions in hardware than can be automated by the first interface.

13. The apparatus of claim 12, wherein the second interface is configured such that less programming code is needed to interact directly with the second interface to effect transmission of data than is needed to interact directly with the first interface to effect a same transmission of data.

14. The apparatus of claim 12, wherein:

the second interface is configured such that less programming code is needed to interact directly with the second interface to process a reception of data than is needed to interact directly with the first interface to process a same reception of data.

15. An apparatus comprising:

a first interface coupled to a first external controller and having;

a communication channel through which data is transmitted to or received from a target device coupled to the first interface by the communication channel; and

a first receive status register that provides a receive buffer status for the first interface to an external controller, the first receive buffer status being in a first data format;

a second interface coupled to the first interface and the first external controller, the second interface having a second receive status register that provides, in a second different format, the receive buffer status to the external controller; and

a circuit coupled to the second interface that transforms contents of the first status register from the first data format to the second different data format, and transforms contents of the second status register from the second different data format to the first data format, such that a same receive buffer status is available to the external controller by both of the first receive status register and the second receive status register.

16. The apparatus of claim 15, wherein the first interface further comprises a buffer that is configured to store data to be transmitted to the target device or data that has been received from the target device.

17. The apparatus of claim 16, wherein the buffer includes a plurality of portions, each portion corresponding to a discrete quantum of data that can be processed by the communication channel at one time.

18. The apparatus of claim 17, wherein the quantum of data is one byte.

19. The apparatus of claim 18, wherein each portion of the plurality of portions is memory-mapped to a discrete address value and individually addressable through the discrete address value by the external controller.

20. The apparatus of claim 19, wherein the second receive status register directly provides at least a portion of the discrete address value when the receive buffer status contained in the second receive status register relates to a buffer portion corresponding to the discrete address value.

21. A method comprising:

controlling a first interface of a first device having a communication channel through which data is transmitted to a second device, the controlling including controlling transmission of data by the first interface and through the communication channel based at least in part on first control data formatted according to a first data format, the first control data specifying updated transmit buffer status data for the first interface;

controlling, using a second interface of the first device, transmission of data by the first interface and through the communication channel, the controlling including controlling transmission of data by the first interface and through the communication channel based at least in part on second control data formatted according to a second different format, the second control data including the updated transmit buffer status data for of the first interface;

translating, to the second different format, first transmit buffer status data formatted according to the first format and stored in a first transmit status register that is associated with the first interface of the first device;

providing the first transmit buffer status data that has been translated to the second different format to a second status register of the second interface;

translating, to the first format, second transmit buffer status data formatted according to the second different format and stored in a second transmit status register that is associated with the second interface of the first device; and

providing the second transmit buffer status data that has been translated to the first format to the first status register of the first interface.

22. The method of claim 21, wherein the second format is configured such that a processor can execute less code to identify a memory portion associated with the transmission or reception of data from the second interface than from the first interface.

23. A method comprising:

receiving, at a device, a digital message from a communication channel;

storing the message in a memory buffer;

storing, in a first receive status register of the device and in a first data format, receive buffer status information in response to storing the message in the memory buffer;

translating, from the first format to a second different format, the receive buffer status information stored in the first receive status register; and

storing, in a second receive status register of the device and in the second different format, the receive buffer status information that has been translated from the first format to the second different format;

wherein a processor of the device executes less code to identify the memory buffer using the receive buffer status information that is formatted according to the second different format than the amount of code that is executed to identify the memory buffer using the receive buffer status information that is formatted according to the first format.

24. The method of claim 23, wherein receiving the digital message comprises receiving the digital message serially, the method further comprising converting the received digital message to a parallel format.

25. The method of claim 23, further comprising extracting a data component from the message.

26. The method of claim 23, further comprising asserting an interrupt signal upon storing the status information or the supplemental status information.