Write once system and method for facilitating digital encrypted transmissions

• US 7,958,376 B2
• Filed: 01/04/2007
• Issued: 06/07/2011
• Est. Priority Date: 11/02/2000
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Glen, David I. J.
• Primary Examiner(s): Patel; Nirav B
• Application Number:
  US11/649,612
• Publication Number:
  US 20070113102A1
• Time in Patent Office: 1,615 Days
• Field of Search: 380200-202, 380/228, 380/277, 380/278, 380/280, 713/193, 713/194, 713/165, 726 26- 30, 711/1, 711/100, 711/128, 711/139, 711/145, 369/13.01, 369/13.56, 369/13.16
• US Class Current: 713/193
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A digital interface device is provided for facilitating key encryption of a digital signal which is communicated from a computer system to an associated peripheral device, such as a digital display device. The digital interface device has a digital output, digital output formatting circuitry associated with the output and a non-volatile RAM for storing a basic input/output system (BIOS) for, inter alia, controlling digital output formatting. The interface device is configured such that the non-volatile RAM has a specific addressable write-protectable area allocated for storing an encryption key flag at a flag address along with encryption key data. The write-protectable area is rendered read-only when a predetermined flag value is stored at the flag address. Thus, encryption key data may be stored in the specific write-protectable area of the non-volatile RAM in connection with storing the predetermined flag at that flag address such that encryption data cannot be altered when the flash RAM is subsequently written to, such as when a BIOS stored in the non-volatile RAM is updated.

Claims

1. A digital device for facilitating use of encryption for digital signals, the interface device comprising:

a non-volatile memory having a write-protectable area allocated for storing an encryption flag at a flag address and encryption data; and

said write-protectable area configured such that it is rendered read-only when a predetermined flag value is stored at said flag address whereby encryption data stored in said write-protectable area of said non-volatile memory cannot be altered by a write operation to said non-volatile memory after said write-protectable area is rendered read-only.

2. A digital device according to claim 1 further comprising:

digital processing circuitry associated with said memory and configured to decrypt encrypted digital signals using encryption data stored in said write-protectable area such that an encrypted signal is decrypted when appropriate encryption data is stored in said write-protectable area.

3. A digital device according to claim 1 configured to store a first predetermined flag value at said flag address in association with encryption data in said specific write-protectable area which first flag value indicates encryption enablement.

4. A digital device according to claim 1 configured to store either a first predetermined flag value at said flag address in association with encryption data in said specific write-protectable area which first flag value indicates encryption enablement or a second predetermined flag value at said flag address which second flag value indicates encryption disablement in which case the digital device is permanently disabled from storing encryption data in said write-protectable area.

5. A digital device according to claim 1 configured to store as said predetermined value any value other than a specific value which specific value enables writing into said write-protectable area.

6. A digital device according to claim 1 wherein said flag is configured as a combination of one or more values stored at the one or more flag addresses within said write-protectable area.

7. A digital device according to claim 1 further comprising:

digital processing circuitry associated with said memory and configured to decrypt encrypted digital video signals using encryption data stored in said write-protectable area such that an encrypted signal is only decrypted when appropriate encryption data is stored in said write-protectable area; and

an output port associated with the digital processing circuitry configured to output a digital video signal.

8. A digital device according to claim 6 which is configured as a digital video interface card.

9. A digital device according to claim 1 wherein said specific writeprotectable area is at least 512 k bytes and located at an address range higher than an address range reserved for a BIOS within said non-volatile memory.

10. The digital device of claim 1 configured to use said predetermined flag value to determine enablement of High bandwidth Digital Content Protection (HDCP) encryption.

11. The digital device of claim 10 configured to store as said encryption data HDCP encryption keys.

12. A method for facilitating the use of digital encryption comprising:

providing a digital device having a non-volatile memory;

allocating a specific addressable area on said non-volatile memory for storing an encryption flag and encryption data; and

rendering said specific area read-only when a predetermined flag value is written in said specific addressable area at a flag address.

13. A method according to claim 12 further comprising:

writing a first predetermined flag value at said flag address along with encryption data in said specific area to enable decryption of a digital signal using the encryption data.

14. A method according to claim 12 further comprising:

writing a first predetermined flag value at said flag address along with encryption data in said specific area to enable key decryption of a digital signal using the encryption data;

or

writing a second predetermined flag value at said flag address to permanently disable decryption using data stored in said specific area.

15. A method according to claim 12 further comprising storing a specific value in said flag address at the time the specific addressable area is allocated wherein said predetermined key value is any value other than said specific value.

16. A method according to claim 12 further comprising providing digital processing circuitry associated with said non-volatile memory and configured to decrypt encrypted digital signals using encryption data stored in said write-protectable area.

17. A configurable device for providing decryption of encrypted signals comprising:

a memory having a write-protectable area allocated for storing an encryption flag at a flag address and encryption data; and

said write-protectable area configured such that it is rendered read-only when a predetermined flag value is stored at said flag address whereby the ability to alter encryption data stored in said write-protectable area of said memory is dependent upon said flag value.

18. The configurable device of claim 17 configured to store as said predetermined flag value at least one of a plurality of predetermined values.

19. The configurable device of claim 17 configured to use said predetermined flag value to determine enablement of High bandwidth Digital Content Protection (HDCP) encryption.

20. The configurable device of claim 19 configured to store as said encryption data HDCP encryption keys.